GWIXP460BAD Intel, GWIXP460BAD Datasheet - Page 25

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GWIXP460BAD

Manufacturer Part Number
GWIXP460BAD
Description
Manufacturer
Intel
Datasheet

Specifications of GWIXP460BAD

Core Operating Frequency
533MHz
Operating Supply Voltage (typ)
1.3/1.5/2.5/3.3V
Operating Supply Voltage (max)
1.575/2.7/3.465V
Operating Supply Voltage (min)
1.235/2.3/3.135V
Package Type
BGA
Pin Count
544
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
Intel
Document Number:
NOTES:
1. Table indicates 32-bit-wide memory subsystem sizes
2. Table indicates 32-bit-wide memory page sizes
DDRI SDRAM
Technology
®
Table 4.
128 Mbit
256 Mbit
IXP45X and Intel
In order to limit double-bit errors from occurring, periodically reading the entire usable memory
array will allow the hardware unit within the memory controller to correct any single-bit, ECC
errors that may have occurred prior to these errors becoming double-bit ECC errors. Using this
method is system-dependent.
It is important to note as well, that when sub-word writes (byte writes or half-word writes) to a
32-bit memory with ECC enabled, the memory controller will implement read-modify writes.
Implementing read-modify writes is important to understand when understanding performance
implications when writing software.
To understand a read-modify write, understanding that a byte to be written falls within a 32-bit
word which is addressed on a word-aligned boundary. When a byte write is requested, the memory
controller will read the 32-bit word which encompasses the byte that is to be written. The memory
controller will then modify the specified byte, calculate a new ECC, and then write the entire 32-bit
word back into the memory location it was read from.
The value written back into the memory location will contain the 32-bit word with the modified
byte and the new ECC value.
The MCU supports two banks of DDR SDRAM. The MCU has support for unbuffered DDRI 266
only.
Table 4
processors. The 128/256/512-Mbit, 1-Gbit DDRI SDRAM devices comprise four internal leaves.
The MCU controls the leaf selects within 128/256/512-Mbit, 1-Gbit DDRI SDRAM by toggling
DDRI_BA[0] and DDRI_BA[1].
The two DDR SDRAM chip enables (DDRI_CS[1:0]#) support a DDRI SDRAM memory
subsystem consisting of two banks. The base address for the two contiguous banks are
programmed in the DDR SDRAM Base Register (SDBR) and must be aligned to a 32-Mbyte
boundary. The size of each DDR SDRAM bank is programmed with the DDR SDRAM boundary
registers (SBR0 and SBR1).
Supported DDRI Memory Configurations (Sheet 1 of 2)
306261-002
DDRI SDRAM
Arrangement
®
16M x 16
IXP46X Product Line of Network Processors Datasheet
16M x 8
8M x 16
32M x 8
illustrates the supported DDR SDRAM configurations for the IXP45X/IXP46X network
# Banks
1
2
1
2
1
2
1
2
Address Size
Row
12
12
13
13
Col
10
10
9
9
DDRI_BA[1]
I_AD[26]
I_AD[25]
I_AD[27]
I_AD[26]
Leaf Select
DDRI_BA[0]
I_AD[25]
I_AD[24]
I_AD[26]
I_AD[25]
Functional Overview
128 Mbyte
128 Mbyte
256 Mbyte
128 Mbyte
64 Mbyte
32 Mbyte
64 Mbyte
64 Mbyte
Memory
Size
Total
1
May 2005
Size
Page
4K
4K
2K
2K
4K
4K
2K
2K
2
25

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