GWIXP460BAD Intel, GWIXP460BAD Datasheet - Page 73

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GWIXP460BAD

Manufacturer Part Number
GWIXP460BAD
Description
Manufacturer
Intel
Datasheet

Specifications of GWIXP460BAD

Core Operating Frequency
533MHz
Operating Supply Voltage (typ)
1.3/1.5/2.5/3.3V
Operating Supply Voltage (max)
1.575/2.7/3.465V
Operating Supply Voltage (min)
1.235/2.3/3.135V
Package Type
BGA
Pin Count
544
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
Package Information
Table 16.
May 2005
73
ETHC_TXCLK
ETHC_TXDATA[3:1]
ETHC_TXDATA[0] /
SMII_TXDATA[5]
ETHC_TXEN
NOTE: This table discusses all features supported on the Intel
† For a legend of the Type codes, see
†† Please refer to Intel
Name
see
Table 1 on page
MII/SMII Interfaces (Sheet 6 of 8)
®
IXP45X and Intel
Power
Reset
on
Z
Z
Z
Z
14.
Reset
VI
0
0
0
Table 10 on page
®
IXP46X Product Line of Network Processors Developer’s Manual for information on how to select the interface desired
Software
Enables
Normal
Reset
After
Until
VO
VO
VO
VI
46.
Software
Enables
Normal
After
®
VO
VO
VO
VI
IXP45X and Intel
Type
O
O
O
I
Externally supplied transmit clock.
This MAC contains hardware hashing capabilities local to the interface.
This signal should be pulled high through a 10-KΩ resistor when being utilized in SMII mode of
operation.
When this interface/signal is enabled and is not being used in a system design, the interface/
signal should be pulled high with a 10-KΩ resistor.
MII Mode of Operation:
Transmit data bus to PHY, asserted synchronously with respect to ETHC_TXCLK. This MAC
contains hardware hashing capabilities local to the interface.
SMII Mode of Operation:
Not used in SMII mode of operation.
MII Mode of Operation:
Transmit data bus to PHY, asserted synchronously with respect to ETHC_TXCLK. This MAC
contains hardware hashing capabilities local to the interface.
SMII Mode of Operation:
The data on this signal is transmitted synchronously with respect to the rising edge of SMII_CLK
when operating as an SMII interface and synchronously with respect to the rising edge of
SMII_TXCLK when operating as a Source Synchronous SMII interface
Indicates that the PHY is being presented with nibbles on the MII interface. Asserted
synchronously, with respect to ETHC_TXCLK, at the first nibble of the preamble, and remains
asserted until all the nibbles of a frame are presented. This MAC contains hardware hashing
capabilities local to the interface.
®
• 25 MHz for 100 Mbps operation
• 2.5 MHz for 10 Mbps
IXP46X Product Line of Network Processors. For details on feature support listed by processor,
Intel
®
IXP45X and Intel
®
Description
IXP46X Product Line of Network Processors Datasheet
Document Number:
306261-002

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