EWIXP420ABBT Intel, EWIXP420ABBT Datasheet - Page 25
Manufacturer Part Number
Specifications of EWIXP420ABBT
Core Operating Frequency
Operating Temperature (max)
Operating Temperature (min)
Operating Temperature Classification
Lead Free Status / Rohs Status
General Hardware Design Considerations—Intel
Document Number: 252817-008US
The SDRAM clock starts with the release of PWRON_RESET_N. The first access made by
the internal auto-refresh counter (set to default value of 0x384) happens ~7µs after
RESET_IN_N is released. Software will not be able to disable this counter before the
first access is made. To meet a specific SDRAMs 100-200 ms requirement before the
first access, the designer may have to add additional delay between PWRON_RESET_N
and RESET_IN_N beyond the required minimum of 10 ns.
The IXP42X product line and IXC1100 control plane processors’ expansion bus supports
a variety of types and speeds of I/O accesses and is specifically designed for
compatibility with Intel and Motorola* microprocessor style bus cycles and the Texas
Instruments* DSP standard Host-Port Interfaces (HPI).
All of these modes are supported seamlessly, without any additional glue logic. Other
cycle types may be supported due to the programmability of the access phases defined
for each cycle type.
The processors’ expansion bus provides a 24-bit address bus and a 16-bit-wide data
interface for each of its eight independent chip-selects and maps transfers between the
internal bus and the external devices. Multiplexed and non-multiplexed address/data
buses are both supported.
Applications having less than 16-bit external data paths may connect to less than the
full 16 bits. Devices with a wider than 16-bit data bus interface are not supported. The
address range of the processors’ expansion bus is from 512 bytes to 16 Mbytes and
provides glueless connection of up to eight independent external devices.
• Software issues a precharge-all command to the SDRAM interface by setting
• Software provides eight auto-refresh cycles. An auto-refresh cycle is accomplished
• Software issues a mode-register-select command by writing to SDR_IR to program
• The memory controller may issue a row activate command three clocks after the
• Software re-enables the refresh counter by setting the SDR_REFRESH to the
SDR_IR to 010
by setting SDR_IR to 100. Software must ensure at least T
auto-refresh command. T
SDRAM being used
the SDRAM parameters. Setting SDR_IR to 000 programs the MCU for CAS latency
of two, while setting the SDR_IR to 001 programs the memory controller and
SDRAM for CAS latency of three.
mode register set command (T
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
IXP42X product line and IXC1100 control
(active to active command period) is determined by the
cycles between each
Hardware Design Guidelines