EWIXP420ABBT Intel, EWIXP420ABBT Datasheet - Page 27

no-image

EWIXP420ABBT

Manufacturer Part Number
EWIXP420ABBT
Description
Manufacturer
Intel
Datasheet

Specifications of EWIXP420ABBT

Core Operating Frequency
533MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EWIXP420ABBT
Manufacturer:
INSTRUMENTS
Quantity:
1 100
Part Number:
EWIXP420ABBT
Manufacturer:
INTEL
Quantity:
220
Part Number:
EWIXP420ABBT
Manufacturer:
INTEL
Quantity:
12
General Hardware Design Considerations—Intel
plane processors
Table 5.
3.2.2.1
December 2007
Document Number: 252817-008US
Expansion Bus Address Description
The chip-level memory map used is determined by the state of bit 31. At system reset
this bit is a ‘1’ and the memory map places the expansion bus at address 0x00000000
through 0x0FFFFFFF. This allows boot code stored in flash to be retrieved and executed
as required.
Once the boot sequence completes this bit is written to a ‘0,’ switching the default
system memory map to place the SDRAM controller at address 0x00000000 to
0x0FFFFFFF. The Expansion Bus Controller now resides at address 0x50000000 to
0x5FFFFFFF. Refer to
The Intel XScale
programmed speed setting. This is done by placing a value on expansion-bus address
bits 23, 22, and 21 at the de-assertion of RESET_IN_N and knowing the speed grade of
the part from the factory. Column 1 of
the part from the factory. Columns 2, 3, and 4 denote the values captured on the
Expansion-Bus address bits at the de-assertion of reset. Column 5 represents the
speed at which the Intel XScale processor speed will operate.
User-Configurable Field
On the Intel
expansion bus address lines for the user-configurable bit-field are internally pulled up.
Users may then change the values by adding weak pull-down resistors (~4.7 kΩ).
Switches can also be used so that changeable values are available for the user
configuration bits.
30:24
23:21
20:17
16:6
Bit
31
5
4
3
2
1
0
®
Intel XScale
IXP42X product line and IXC1100 control plane processors, the
®
Clock Set[2:0]
8/16 FLASH
PCI_HOST
MEM_MAP
Processor can operate at slower speeds than the factory-
PCI_ARB
PCI_CLK
Intel
Name
Table 1 on page 17
®
®
Processor
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
®
IXP42X product line and IXC1100 control
Location of Expansion Bus in memory map space:
0 = Located at “50000000” (normal mode)
1 = Located at “00000000” (boot mode)
(Reserved)
Allow a slower Intel XScale
device fuse settings; however, cannot be used to over-clock
processor speed. Refer to
details.
User-configurable. See
(Reserved)
(Reserved)
Enables the clock speed of the PCI Interface
0 = 33 MHz
1 = 66 MHz
(Reserved) EX_ADDR[3] must not be pulled down during address
strapping. This bit must be written to ‘1’ if performing a write to
this register.
Enables the PCI Controller Arbiter
0 = PCI arbiter disabled
1 = PCI arbiter enabled
Configures the PCI Controller as PCI Bus Host
0 = PCI as non-host
1 = PCI as host
Specifies the data bus width of the flash memory device
0 = 16-bit data bus
1 = 8-bit data bus
Table 30 on page 88
for the complete memory map.
Section 3.2.2.1
Table 30 on page
Description
®
Processor clock speed to override
denotes the speed grade of
for further details.
Hardware Design Guidelines
88, for additional
27