EWIXP420ABBT Intel, EWIXP420ABBT Datasheet - Page 41
Manufacturer Part Number
Specifications of EWIXP420ABBT
Core Operating Frequency
Operating Temperature (max)
Operating Temperature (min)
Operating Temperature Classification
Lead Free Status / Rohs Status
General Hardware Design Considerations—Intel
Document Number: 252817-008US
For explanations of the
Interface Signals (Sheet 2 of 2)
UTOPIA Input Data flow control input signal. Also known as RXEMPTY/CLAV.
Used to inform the
cell-level flow control in an MPHY environment, RxClav is an active-high tri-stateable signal
from the MPHY to ATM layer. The UTP_IP_FCI, which is connected to multiple MPHY devices,
will see logic high generated by the PHY, one clock after the given PHY address is asserted,
when a full cell can be received by the PHY. The UTP_IP_FCI will see a logic low generated by
the PHY, one clock cycle after the PHY address is asserted if a full cell cannot be received by
In SPHY mode, this signal is used to indicate to the processor that the PHY has an octet or cell
available to be transferred to the processor.
The signal should be tied high through a 10-kΩ resistor when not being used in the system.
Start of Cell. RX_SOC
Active-high signal that is asserted when UTP_IP_DATA contains the first valid byte of a
The signal should be pulled high through a 10-kΩ resistor, when not being used in the system.
UTOPIA input data. Also known as RX_DATA.
Used by to the processor to receive data from an ATM UTOPIA-Level-2-compliant PHY.
Should be tied high through a 10-kΩ resistor, when not being used in the system.
Receive PHY address bus.
Used by the processor when operating in MPHY mode to poll and select a single PHY at any
one given time.
UTOPIA Input Data Flow Control Output signal: Also known as the RX_ENB_N.
In SPHY configurations, UTP_IP_FCO is used to inform the PHY that the processor is ready to
In MPHY configurations, UTP_IP_FCO is used to select which PHY will drive the UTP_RX_DATA
and UTP_RX_SOC signals. The PHY is selected by placing the PHY’s address on the
UTP_IP_ADDR and bringing UTP_OP_FCO to logic 1 during the current clock, followed by the
UTP_OP_FCO going to a logic 0 on the next clock cycle.
column abbreviations, see
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
IXP42X product line and IXC1100 control
of the ability of each polled PHY to send a complete cell. For
Table 21 on page
Hardware Design Guidelines