EWIXP420ABBT Intel, EWIXP420ABBT Datasheet - Page 43

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EWIXP420ABBT

Manufacturer Part Number
EWIXP420ABBT
Description
Manufacturer
Intel
Datasheet

Specifications of EWIXP420ABBT

Core Operating Frequency
533MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Compliant

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General Hardware Design Considerations—Intel
plane processors
3.9.1
December 2007
Document Number: 252817-008US
Interface Signals
HSS_TXFRAME1
HSS_TXDATA1
HSS_TXCLK1
HSS_RXFRAME1
HSS_RXDATA1
HSS_RXCLK1
HSS_TXFRAME0
HSS_TXDATA0
HSS_TXCLK0
Note:
Name
For explanations of the
Type
O/D
O/D
I/O
I/O
I/O
I/O
I/O
I/O
Intel
I
®
The High-Speed Serial (HSS) transmit frame signal can be configured as an input
or an output to allow an external source to be synchronized with the transmitted
data. Often known as a Frame Sync signal. Configured as an input upon reset.
Should be pulled high through a 10-kΩ resistor when not being used in the
system.
Transmit data out. Open-drain output.
Must be pulled up with a 10-kΩ resistor to V
The High-Speed Serial (HSS) transmit clock signal can be configured as an input
or an output. The clock can be a frequency ranging from 512 KHz to 8.192 MHz.
Used to clock out the transmitted data. Configured as an input upon reset.
Frame sync and Data can be selected to be generated on the rising or falling
edge of the transmit clock.
Should be pulled high through a 10-kΩ resistor when not being used in the
system.
The High-Speed Serial (HSS) receive frame signal can be configured as an input
or an output to allow an external source to be synchronized with the received
data. Often known as a Frame Sync signal. Configured as an input upon reset.
Should be pulled high through a 10-kΩ resistor when not being used in the
system.
Receive data input. Can be sampled on the rising or falling edge of the receive
clock.
Should be pulled high through a 10-kΩ resistor when not being used in the
system.
The High-Speed Serial (HSS) receive clock signal can be configured as an input
or an output. The clock can be from 512 KHz to 8.192 MHz. Used to sample the
received data. Configured as an input upon reset.
Should be pulled high through a 10-kΩ resistor when not being used in the
system.
The High-Speed Serial (HSS) transmit frame signal can be configured as an input
or an output to allow an external source become synchronized with the
transmitted data. Often known as a Frame Sync signal. Configured as an input
upon reset.
Should be pulled high through a 10-kΩ resistor when not being used in the
system.
Transmit data out. Open-drain output.
Must be pulled up with a 10-kΩ resistor to V
The High-Speed Serial (HSS) transmit clock signal can be configured as an input
or an output. The clock can be a frequency ranging from 512 KHz to 8.192 MHz.
Used to clock out the transmitted data. Configured as an input upon reset.
Frame sync and data can be selected to be generated on the rising or falling
edge of the transmit clock.
Should be pulled high through a 10-kΩ resistor when not being used in the
system.
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Type
®
IXP42X product line and IXC1100 control
column abbreviations, see
Description
Table 21 on page
CCP
CCP
.
.
Hardware Design Guidelines
81.
43