EWIXP420ABBT Intel, EWIXP420ABBT Datasheet - Page 45

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EWIXP420ABBT

Manufacturer Part Number
EWIXP420ABBT
Description
Manufacturer
Intel
Datasheet

Specifications of EWIXP420ABBT

Core Operating Frequency
533MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Compliant

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12
General Hardware Design Considerations—Intel
plane processors
3.10.1
Table 11.
December 2007
Document Number: 252817-008US
PCI Interface Signals
PCI Bus Signals (Sheet 1 of 2)
Note:
PCI_REQ_N[3:1]
PCI_CBE_N[3:0]
PCI_DEVSEL_N
PCI_FRAME_N
PCI_AD[31:0]
PCI_TRDY_N
PCI_STOP_N
PCI_PERR_N
PCI_SERR_N
PCI_IRDY_N
PCI_IDSEL
PCI_PAR
For explanations of the
Name
Intel
®
Type*
I/OD
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
Type
®
IXP42X product line and IXC1100 control
PCI Address/Data bus used to transfer address and bidirectional data
to and from multiple PCI devices.
Should be pulled high with a 10-kΩ resistor when the PCI bus is not
being used in the system.
PCI Command/Byte Enables used as a command word during an PCI
address cycles and byte enables for data cycles.
Should be pulled high with a 10-kΩ resistor when the PCI bus is not
being used in the system.
PCI Parity used to check parity across the 32 bits of PCI_AD and the
four bits of PCI_CBE_N.
Should be pulled high with a 10-kΩ resistor when not being used in
the system.
PCI Cycle Frame used to signify the beginning and duration of a
transaction. The signal will be inactive prior to or during the final data
phase of a given transaction.
Should be pulled high with a 10-kΩ resistor when the PCI bus is not
being used in the system.
PCI Target Ready informs that the target of the PCI bus is ready to
complete the current data phase of a given transaction.
Should be pulled high with a 10-kΩ resistor when the PCI bus is not
being used in the system.
PCI Initiator Ready informs that the initiator to complete the current
data phase of a given transaction.
Should be pulled high with a 10-kΩ resistor when the PCI bus is not
being used in the system.
PCI Stop indicates that the current target is requesting the current
initiator to stop the current transaction.
Should be pulled high with a 10-kΩ resistor when the PCI bus is not
being used in the system.
PCI Parity Error is asserted when a PCI parity error is detected
between the PCI_PAR and the associated information on the PCI_AD
bus and PCI_CBE_N during all PCI transactions except for special
cycles. The agent that is receiving data will drive this signal.
Should be pulled high with a 10-kΩ resistor when the PCI bus is not
being used in the system.
PCI System Error asserted when a parity error occurs on special cycles
or any other error that will cause the PCI bus not to function properly.
Should be pulled high with a 10-kΩ resistor when the PCI bus is not
being used in the system.
PCI Device Select:
Should be pulled high with a 10-kΩ resistor when not being used in
the system.
PCI Initialization Device Select is a chip select during configuration
reads and writes.
Should be pulled high with a 10-kΩ resistor when the PCI bus is not
being used in the system.
PCI arbitration request: Used by the internal PCI arbiter to allow an
agent to request the PCI bus.
Should be pulled high with a 10-kΩ resistor when the PCI bus is not
being used in the system.
column abbreviations, see
• When used as an output, PCI_DEVSEL_N indicates that device has
• When used as an input, PCI_DEVSEL_N indicates if any device on
decoded that address as the target of the requested transaction.
the PCI bus exists with the given address.
Table 21 on page
Description
Hardware Design Guidelines
81.
45