EWIXP420ABBT Intel, EWIXP420ABBT Datasheet - Page 46

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EWIXP420ABBT

Manufacturer Part Number
EWIXP420ABBT
Description
Manufacturer
Intel
Datasheet

Specifications of EWIXP420ABBT

Core Operating Frequency
533MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Compliant

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Table 11.
Intel
Hardware Design Guidelines
46
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
PCI Bus Signals (Sheet 2 of 2)
Note:
PCI_GNT_N[3:1]
PCI_GNT_N[0]
PCI_REQ_N[0]
PCI_INTA_N
PCI_CLKIN
Intel
For explanations of the
Name
®
IXP42X product line and IXC1100 control plane processors—General Hardware Design
Type*
O/D
I/O
I/O
O
I
Type
PCI arbitration request:
Should be pulled high with a 10-kΩ resistor, when the PCI bus is not
being used in the system.
PCI arbitration grant: Generated by the internal PCI arbiter to allow an
agent to claim control of the PCI bus.
PCI arbitration grant:
Should be pulled high with a 10-kΩ resistor when not being used in
the system.
PCI interrupt: Used to request an interrupt.
Should be pulled high with a 10-kΩ resistor.
PCI Clock: Clock provides timing for all transactions on PCI. All PCI
signals, except INTA#, INTB#, INTC#, and INTD#, are sampled on
the rising edge of CLK and timing parameters are defined with respect
to this edge. The PCI clock rate can operate at up to 66 MHz.
Should be pulled high with a 10-kΩ resistor when the PCI bus is not
used in the system.
column abbreviations, see
• When configured as an input (PCI arbiter enabled), the internal
• When configured as an output (PCI arbiter disabled), the pin will
• When configured as an output (PCI arbiter enabled), the internal
• When configured as an input (PCI arbiter disabled), the pin will be
PCI arbiter will allow an agent to request the PCI bus.
be used to request access to the PCI bus from an external arbiter.
PCI arbiter to allow an agent to claim control of the PCI bus.
used to claim access of the PCI bus from an external arbiter.
Table 21 on page
Description
Document Number: 252817-008US
81.
Considerations
December 2007