EWIXP420ABBT Intel, EWIXP420ABBT Datasheet - Page 5

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EWIXP420ABBT

Manufacturer Part Number
EWIXP420ABBT
Description
Manufacturer
Intel
Datasheet

Specifications of EWIXP420ABBT

Core Operating Frequency
533MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Compliant

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Contents—Intel
Figures
December 2007
Document Number: 252817-008US
1
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38
A.9
A.10 Oscillator Interface ............................................................................................ 89
A.11 GPIO Interface.................................................................................................. 90
A.12 JTAG Interface .................................................................................................. 90
A.13 System Interface............................................................................................... 90
A.14 Power Interface ................................................................................................ 91
A.15 V
A.16 Common Issues ................................................................................................ 94
A.17 Design Considerations........................................................................................ 95
Devices’ Component Block Diagram ............................................................................ 14
Devices’ System Block Diagram ................................................................................. 16
Dual-Bank SDRAM System Block Diagram (x32 Devices) ............................................... 22
Single Bank SDRAM System Block Diagram (x16 Devices) ............................................. 23
Dual Bank SDRAM System Block Diagram (x16 Devices) ............................................... 24
Expansion Bus Flash Interface ................................................................................... 28
Expansion Bus SRAM Interface................................................................................... 29
Fast UART Interface ................................................................................................. 31
Console UART Interface ............................................................................................ 32
MII Block Diagram ................................................................................................... 35
I
USB Interface .......................................................................................................... 39
UTOPIA Interface ..................................................................................................... 42
HSS Interface .......................................................................................................... 44
PCI Interface ........................................................................................................... 47
Clock Connections .................................................................................................... 50
Power-up Sequence Timing ....................................................................................... 52
Reset Timings.......................................................................................................... 52
492-Ball PBGA Package............................................................................................. 55
Devices’ Signals by Function ...................................................................................... 56
Component Placement on a PCB................................................................................. 58
8-Layer Stackup ...................................................................................................... 60
6-Layer Stackup ...................................................................................................... 60
Good Design Practice for VIA Hole Placement............................................................... 62
Poor Design Practice for VIA Placement ....................................................................... 62
Pad-to-Pad Clearance of Passive Components to a PGA or BGA....................................... 63
Signal Changing Reference Planes .............................................................................. 64
SDRAM Topology ..................................................................................................... 73
SDRAM Clock Topology ............................................................................................. 75
PCI Address/Data Topology ....................................................................................... 76
PCI Address/Data Topology (PCI Bridge to cPCI Bridge Connector) ................................. 77
PCI Clock Topology .................................................................................................. 77
Typical Connection to an Oscillator ............................................................................. 89
RCOMP Pin External Resistor Requirements ................................................................. 91
V
V
V
V
2
CCPLL1
CCPLL2
CCOSCP
CCOSC
C EEPROM Interface............................................................................................... 37
USB Interface ................................................................................................... 89
A.10.1 Oscillator Interface ................................................................................. 89
A.13.1 RCOMP Pin Requirements ........................................................................ 91
A.15.1 V
A.15.2 V
A.15.3 V
A.15.4 V
®
CCPLL1
IXP42X product line and IXC1100 control plane processors
Power Filtering Diagram ................................................................................. 94
Power Filtering Diagram................................................................................. 92
Power Filtering Diagram................................................................................. 93
Power Filtering Diagram ................................................................................ 93
, V
CCPLL1
CCPLL2
CCOSCP
CCOSC
CCPLL2
Requirement ............................................................................... 93
Requirement............................................................................... 92
Requirement............................................................................... 92
, V
Requirement.............................................................................. 93
CCOSCP
Intel
®
, V
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
CCOSC
Pin Requirements .............................................. 92
Hardware Design Guidelines
5