EWIXP420ABBT Intel, EWIXP420ABBT Datasheet - Page 51

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EWIXP420ABBT

Manufacturer Part Number
EWIXP420ABBT
Description
Manufacturer
Intel
Datasheet

Specifications of EWIXP420ABBT

Core Operating Frequency
533MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Compliant

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General Hardware Design Considerations—Intel
plane processors
Table 14.
3.13.1
3.13.2
3.13.3
3.13.4
Note:
Note:
December 2007
Document Number: 252817-008US
Power Pins (Sheet 2 of 2)
To enable low power system design, the IXP42X product line and IXC1100 control plane
processors have separate power supply domains for the processor core, SDRAM
memory, and peripherals.
Power Supply Requirements
The main power supply domains for the IXP42X product line and IXC1100 control plane
processors are 1.3 V (VCC) for the Intel XScale
signaling voltage.
+3.3 V DC
It is suggested that the +3.3-V supply tolerance is +/-5% and a maximum current of
3 A and is provided by an on-board DC-DC switch-mode voltage regulator.
+1.3 V DC
The +1.3V DC needed for the Intel XScale
switch-mode voltage regulator and derived from the +3.3-V rail.
Power Up
The 3.3-V I/O voltage (V
(V
must never become stable prior to the 3.3-V I/O voltage (V
and V
power-up pattern. The value for T
parameter is measured from V
The PWRON_RESET_N signal is a 1.3-V signal.
The SDRAM clock starts with the release of PWRON_RESET_N. The first access made by
the internal auto-refresh counter (set to default value of 0x384) happens ~7µs after
RESET_IN_N is released. Software will not be able to disable this counter before the
first access is made. To meet a specific SDRAMs 100-200 ms requirement before the
first access, the designer may have to add additional delay between PWRON_RESET_N,
and RESET_IN_N beyond the required minimum of 10 ns.
Figure 17
Note:
VCCPLL1
VCCPLL2
CC
Name
). The IXP42X product line and IXC1100 control plane processors’ voltage (V
CCPLL2
For explanations of the
and
voltages follow the V
Type*
Figure 18
I
I
Intel
1.3
loop circuitry on IXP42X product line and IXC1100 control plane processors. Require
special power-filtering circuitry. Refer to the Intel
Processors and IXC1100 Control Plane Processor Datasheet for proper
implementation.
1.3
loop circuitry on IXP42X product line and IXC1100 control plane processors. Refer to
theIntel
Processor Datasheet for proper implementation.
-
-
®
V power supply input pins used for the internal logic of the analog, phase-lock
V power supply input pins used for the internal logic of the analog, phase-lock
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
show the relationship between power up, and reset timings.
CCP
®
Type
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane
) must be powered up 1 µs before the processor voltage
IXP42X product line and IXC1100 control
CCP
column abbreviations, see
CC
POWER_UP
at 3.3 V and V
power-up pattern. The V
®
must be at least 1
Processor can be generated using a DC-DC
®
Description
CC
Processor and 3.3 V (VCCP) for I/O
at 1.3 V.
Table 21 on page
®
CCP
IXP42X Product Line of Network
CCOSCP
µ
). The V
s. The T
Hardware Design Guidelines
81.
follows the V
POWER_UP
CCOSC
, V
CCPLL1
timing
CCP
CC
)
,
51