EWIXP420ABBT Intel, EWIXP420ABBT Datasheet - Page 66

• Manufacturer Part Number: EWIXP420ABBT
• Manufacturer: Intel

Specifications of EWIXP420ABBT

• Core Operating Frequency: 533MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

6.3.2
Intel
Hardware Design Guidelines
66
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IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
LAN Signal Considerations
• Maintain impedance control for all clock traces. Calculate the impedance for both
• Measure the actual routed trace lengths of all clocks and determine if the actual
• Route clock traces on one routing layer only, adjacent to a solid plane. If possible,
• Keep the two traces in a differential pair close to each other. Ideally, traces should
• Wherever possible, use a perfect symmetry within a differential pair; use equal
• Wherever possible, minimize discontinuities. Discontinuities are caused by solder
• Avoid routing other signals close by and/or parallel to differential pairs. No signal
• Avoid routing high-speed LAN or telephone-line traces near other high-frequency
• If there is a ground-fill or power-fill within 30 mils of one side of a differential pair,
• For LAN designs, the length of the differential traces between the transformer’s
microstrip and stripline.
routed length is longer than maximum allowable calculated length. If so,
termination is required.
route all clock traces on stripline.
be within 30 mils (edge-to-edge). Except within 0.5 inches of entering an
integrated circuit or a magnetics, or connector solder pads, the distance between
the two traces should be kept uniform. It is important to keep the two traces within
a differential pair close to each other. Keeping them close helps to make them more
immune to crosstalk and other sources of common-mode noise. Keeping them
close means lower emissions (for FCC compliance) from the transmit traces, and
better receive BER for the receive traces. Close should be considered to be less
than 0.030 inches between the two traces within a differential pair. 0.008 inch to
0.012 inch trace-to-trace spacing is recommended.
lengths/distances to any vias or common components.
pads, test points, vias, changes in trace-to-trace spacing, and changes in trace
width.
should be closer to a differential pair than 0.100 inches.
signals associated with a video controller, cache controller, CPU, or other similar
devices.
then there must be a very similar fill the same distance away on the other side of
the differential pair.
solder pads to the PHY’s transmit and receive solder pads should preferably be less
than three inches, and never more than four inches.
Intel
— Keep impedances of clock traces balanced and short to minimize reflections and
— Be aware of the propagation delay of signal traces for both microstrip and
— Calculate capacitive loading of all components and properly compensate with a
— With the current circuit speeds, all clock signals require termination. If traces
— Microstrip allows for fastest transition of signal edges while permitting greater
functionality degradation. The wider the trace, the lower the impedance
presented to the circuit.
stripline.
series resistor and/or an end termination.
must be electrically long, route the traces using transmission line theory.
terminate all clock traces in their characteristic impedance.
amount of RF currents to be radiated from the trace. Stripline allows for
optimal suppression of RF currents, but at the expense of slowing down signal
edges (picoseconds) due to capacitive loading between the trace and
surrounding planes. Routing in internal layers reduces EMI by about 20 dB.
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IXP42X product line and IXC1100 control plane processors—General Layout and Routing
Document Number: 252817-008US
December 2007
Guide