EWIXP420ABBT Intel, EWIXP420ABBT Datasheet - Page 87

• Manufacturer Part Number: EWIXP420ABBT
• Manufacturer: Intel

Specifications of EWIXP420ABBT

• Core Operating Frequency: 533MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

Design Checklist—Intel
Table 28.
A.7.1
Table 29.
December 2007
Document Number: 252817-008US
Expansion Bus Interface (Sheet 2 of 2)
Expansion Bus Configuration Strappings
At power up or whenever a reset is asserted, the expansion-bus address outputs are
switched to inputs and the states of the bits are captured and stored in Configuration
Register 0, bits 23 through 0. This occurs on the first cycle after the synchronous de-
assertion of the reset signal.
The Expansion Bus address bit all have internal pull-up resistors. Each bit may be
pulled low by placing a pull-down resistor on the address signal.
These configuration bits are made available to the system as outputs from the
Expansion Bus Controller block. With the exception of bits 23, 22 and 21, which are
read only, all other bits may be written and read from the South AHB.
Expansion Bus Configuration Register 0 (Sheet 1 of 2)
EX_CS_N[7:0]
EX_DATA[15:0]
EX_IOWAIT_N
EX_RDY[3:0]
†
††
23:21
20:17
®
16:6
Name
Bit
5
4
3
2
1
IXP42X product line and IXC1100 control plane processors
For a legend of the
For new designs, this signal should be pulled high with a 10-KΩ resistor when not being utilized in the
system. No change is required to existing designs that have this signal pulled low.
Intel XScale
Type
Intel
I/O
O
I
I
Clock Set[2:0]
†
®
PCI_HOST
Type
PCI_ARB
PCI_CLK
Name
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
External chip selects for expansion bus.
Chip selects 0 through 7 can be configured to support Intel or
Motorola bus cycles.
Chip selects 4 through 7 can be configured to support TI* HPI
bus cycles.
No external circuitry needed,
Should be pulled high through a 10-KΩ resistor when not being
utilized in the system.
When configured to operate in HPI mode there is one RDY signal
per chip select. This signal only affects accesses that use
EX_CS_N[7:4].
Should be pulled high
utilized in the system.
®
Processor
codes, see
Table 21 on page
Allow a slower Intel XScale
override device fuse settings. However cannot be used to
overclock processor speed. For additional details, see
Table 30 on page
User Configurable
(Reserved)
(Reserved)
Sets the PCI Controller Speed.
(Reserved) EX_ADDR[3] must not be pulled down during
address strapping. This bit must be written to ‘1’ if
performing a write to this register.
Enables the PCI Controller Arbiter.
Configures the PCI Controller as PCI Bus Host.
• 0 = 33 MHz
• 1 = 66 MHz
• 0 = PCI arbiter disabled
• 1 = PCI arbiter enabled
• 0 = PCI as non-host
• 1 = PCI as host
††
Recommendation
though a 10-KΩ resistor when not being
81.
88.
Description
®
Processor clock speed to
Hardware Design Guidelines
Complete?
87