EWIXP420ABBT Intel, EWIXP420ABBT Datasheet - Page 94

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EWIXP420ABBT

Manufacturer Part Number
EWIXP420ABBT
Description
Manufacturer
Intel
Datasheet

Specifications of EWIXP420ABBT

Core Operating Frequency
533MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Compliant

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Figure 38.
A.16
Intel
Hardware Design Guidelines
94
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
V
In order to achieve a 200-nF capacitance, a parallel combination of two 100-nF
capacitors may be used as long as the capacitors are placed directly beside each other.
Common Issues
Completing the checklist in
schematics prior to manufacturing a system board that implements an Intel
Product Line of Network Processors and IXC1100 Control Plane Processor. This section
highlights some commonly overlooked issues that deserve extra attention as they could
be a “show-stopper” if handled incorrectly.
The following points should be reviewed prior to manufacturing:
• The PWRON_RST_N signal is a 1.3-V signal.
• The JTG_TRST_N signal must be asserted during reset to properly initialize the TAP
• If either MII interface has been used, the ENET_MDIO signal must be pulled high
• The RCOMP signal, pin D25, requires a 34-Ω +/- 1% tolerance pull-down resistor.
• The phase-lock loop circuits (V
• The 3.3-V I/O voltage (V
• Ensure that the proper Expansion Bus Configuration Resistors are populated.
• Ensure that the proper SDRAM Chip Select was used to access either common or
CCOSC
This signal should not be pulled up to 3.3 V.
controller.
This signal should be pulled low using a 10-KΩ resistor.
with a 1.5-KΩ resistor.
(See
and V
1.3-V signals.
It is important to note that V
in
voltage (V
The IXP42X product line and IXC1100 control plane processors’ voltage (V
never become stable prior to the 3.3-V I/O voltage (V
sequencing requirements, given in the Intel
Processors and IXC1100 Control Plane Processor Datasheet, should be reviewed.
For more detail, see
page
different SDRAM banks.
Section
Power Filtering Diagram
Figure 34 on page
87.
CCOSC
CC
Intel
1.3 V
A.15.
) require isolated voltage supplies. V
10 nF
).
®
V
IXP42X product line and IXC1100 control plane processors—Design Checklist
SS
Section A.7.1, “Expansion Bus Configuration Strappings” on
100 nF
Section A.1, “Checklist” on page 81
91.)
CCP
) must be powered up 1 µs before the processor
CCOSCP
CCPLL1
is a 3.3-V signal. Detailed information is shown
and V
100 nF
CCPLL2
®
IXP42X Product Line of Network
CCPLL1
) and oscillator circuit (V
CCP
,
Intel
Product Line /
Intel
Control Plane
V
Document Number: 252817-008US
Processor
CCPLL2
). The complete power-
®
®
IXC1100
IXP42X
helps the user review
and V
B1676-03
CCOSC
December 2007
®
CCOSCP
CC
IXP42X
are
) must