EWIXP420ABBT Intel, EWIXP420ABBT Datasheet - Page 94
Manufacturer Part Number
Specifications of EWIXP420ABBT
Core Operating Frequency
Operating Temperature (max)
Operating Temperature (min)
Operating Temperature Classification
Lead Free Status / Rohs Status
Hardware Design Guidelines
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
In order to achieve a 200-nF capacitance, a parallel combination of two 100-nF
capacitors may be used as long as the capacitors are placed directly beside each other.
Completing the checklist in
schematics prior to manufacturing a system board that implements an Intel
Product Line of Network Processors and IXC1100 Control Plane Processor. This section
highlights some commonly overlooked issues that deserve extra attention as they could
be a “show-stopper” if handled incorrectly.
The following points should be reviewed prior to manufacturing:
• The PWRON_RST_N signal is a 1.3-V signal.
• The JTG_TRST_N signal must be asserted during reset to properly initialize the TAP
• If either MII interface has been used, the ENET_MDIO signal must be pulled high
• The RCOMP signal, pin D25, requires a 34-Ω +/- 1% tolerance pull-down resistor.
• The phase-lock loop circuits (V
• The 3.3-V I/O voltage (V
• Ensure that the proper Expansion Bus Configuration Resistors are populated.
• Ensure that the proper SDRAM Chip Select was used to access either common or
This signal should not be pulled up to 3.3 V.
This signal should be pulled low using a 10-KΩ resistor.
with a 1.5-KΩ resistor.
It is important to note that V
The IXP42X product line and IXC1100 control plane processors’ voltage (V
never become stable prior to the 3.3-V I/O voltage (V
sequencing requirements, given in the Intel
Processors and IXC1100 Control Plane Processor Datasheet, should be reviewed.
For more detail, see
different SDRAM banks.
Power Filtering Diagram
Figure 34 on page
) require isolated voltage supplies. V
IXP42X product line and IXC1100 control plane processors—Design Checklist
Section A.7.1, “Expansion Bus Configuration Strappings” on
Section A.1, “Checklist” on page 81
) must be powered up 1 µs before the processor
is a 3.3-V signal. Detailed information is shown
IXP42X Product Line of Network
) and oscillator circuit (V
Product Line /
Document Number: 252817-008US
). The complete power-
helps the user review