PRIXP423ABD Intel, PRIXP423ABD Datasheet - Page 98

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PRIXP423ABD

Manufacturer Part Number
PRIXP423ABD
Description
Manufacturer
Intel
Datasheet

Specifications of PRIXP423ABD

Core Operating Frequency
533MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
Table 56.
Intel
Datasheet
98
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Intel
Talepulse
Tale2addrhold
Tdval2valwrt
Twrpulse
Tdholdafterwr
Tale2valcs
Trdsetup
Trdhold
Trecov
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Symbol
®
The EX_ALE signal is extended from 1 to 4 cycles based on the programming of the T1 timing
parameter. The parameter Tale2addrhold is fixed at 1 cycle.
Setting the address phase parameter (T1) will adjust the duration that the address appears to the
external device.
Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a
data strobe (read or write) to an external device.
Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears
(read or write) to an external device. Data will be available during this time as well.
Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects,
address, and data (during a write) will be held.
Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
expansion interface.
One cycle is the period of the Expansion Bus clock.
Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in
synchronous mode.
Timing tests were performed with a 70-pF capacitor to ground.
Multiplexed Mode Values
Pulse width of EX_ALE (ADDR is valid at the rising edge of
EX_ALE)
Valid address hold time after from falling edge of EX_ALE
Write data valid prior to EX_WR_N falling edge
Pulse width of the EX_WR_N
Valid data after the rising edge of EX_WR_N
Valid chip select after the falling edge of EX_ALE
Data valid required before the rising edge of EX_RD_N
Data hold required after the rising edge of EX_RD_N
Time needed between successive accesses on expansion
interface.
Intel
®
IXP42X product line and IXC1100 control plane processors—Datasheet
Parameter
Document Number:
Min.
15
1
1
1
1
1
1
0
1
Max.
16
16
4
1
4
4
4
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Units
252479-007US
ns
ns
June 2007
Notes
1, 2,
1,
3,
4,
5,
7
6
7
7
7
7
7

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