AD9726BSVZ Analog Devices Inc, AD9726BSVZ Datasheet - Page 5
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AD9726BSVZ
Manufacturer Part Number
AD9726BSVZ
Description
IC DAC 16IT LVDS 400MSPS 80-TQFP
Manufacturer
Analog Devices Inc
Series
TxDAC+®r
Datasheet
1.AD9726BSVZRL.pdf
(24 pages)
Specifications of AD9726BSVZ
Data Interface
Parallel
Number Of Bits
16
Number Of Converters
1
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
575mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
Resolution (bits)
16bit
Sampling Rate
400MSPS
Input Channel Type
Parallel
Supply Current
80mA
Digital Ic Case Style
QFP
No. Of Pins
80
Package
80TQFP EP
Resolution
16 Bit
Conversion Rate
400 MSPS
Digital Interface Type
Parallel
Number Of Outputs Per Chip
1
Output Type
Current
Full Scale Error
0.003(Typ) %FSR
Integral Nonlinearity Error
±2.5 LSB
Maximum Settling Time
0.0105(Typ) us
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9726-EBZ - BOARD EVAL FOR AD9726
Settling Time
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD9726BSVZ
Manufacturer:
Epson
Quantity:
1 271
Company:
Part Number:
AD9726BSVZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Company:
Part Number:
AD9726BSVZRL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
DIGITAL SIGNAL SPECIFICATIONS
DBVDD = AVDD1 = AVDD2 = 3.3 V, DVDD = CLKVDD = ADVDD = ACVDD = 2.5 V, I
T
Table 3.
Parameter
DAC CLOCK INPUTS (CLK±)
LVDS INPUTS (DB[15:0]±, DCLK_IN±)
LVDS OUTPUT (DCLK_OUT±)
CMOS INPUTS (CSB, SCLK, SDIO, RESET)
CMOS OUTPUTS (SDO, SDIO)
CONTROL INPUTS (SPI_DIS, SDR_EN)
1
TIMING SPECIFICATIONS
DBVDD = AVDD1 = AVDD2 = 3.3 V, DVDD = CLKVDD = ADVDD = ACVDD = 2.5 V, I
T
Table 4.
Parameter
LVDS DATA BUS
With 100 Ω external load.
MIN
MIN
Differential Voltage
Common-Mode Voltage
Input Voltage Range
Differential Threshold Voltage
Differential Input Impedance
Differential Output Voltage
Offset Voltage
Short-Circuit Output Current
Logic 0 Voltage
Logic 1 Voltage
Input Current
Logic 0 Voltage
Logic 1 Voltage
Short-Circuit Output Current
Logic 0 Voltage
Logic 1 Voltage
Input Current
Data Synchronization Enabled (Default)
Data Synchronization Bypassed
DDR DCLK_OUT± Propagation Delay (t
DDR DB[15:0]± Setup Time (t
DDR DB[15:0]± Hold Time (t
SDR DCLK_OUT± Propagation Delay (t
SDR DB[15:0]± Setup Time (t
SDR DB[15:0]± Hold Time (t
DB[15:0]± Setup Time (t
DB[15:0]± Hold Time (t
CLK± to IOUT Propagation Delay (t
DB[15:0]± to IOUT Pipeline Delay (t
to T
to T
MAX
MAX
, unless otherwise specified.
, unless otherwise specified.
DH-BYPASS
DSU-BYPASS
1
DH-SDR
DH-DDR
DSU-SDR
DSU-DDR
)
)
)
)
)
PD-BYPASS
)
PIPE-BYPASS
DCPD-SDR
DCPD-DDR
)
)
)
)
Rev. B | Page 5 of 24
−100
−100
Min
825
250
Min
500
500
800
0.5
1.0
1.0
2.5
3.0
2.0
50
OUT-FS
OUT-FS
1.25
Typ
100
400
0.85
Typ
1.0
1.2
20
10
1
1
4
= 20 mA, internal reference,
= 20 mA, internal reference,
1575
2000
Max
Max
100
300
0.5
0.5
0.5
Unit
V
V
mV
mV
Ω
mV
V
mA
V
V
nA
V
V
mA
V
V
nA
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ns
DAC clock cycles
AD9726