TXC-06312BIOG Transwitch Corporation, TXC-06312BIOG Datasheet - Page 12

• Manufacturer Part Number: TXC-06312BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06312BIOG

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PRELIMINARY TXC-06312B-MB, Ed. 2
June 2005
PHAST-12N Device
DATA SHEET
TXC-06312B
The TranSwitch PHAST-12N is a highly integrated STM-4/OC-12 rate SDH/SONET overhead
termination device designed for TDM payload mappings. A single PHAST-12N can terminate
four individual STM-1/OC-3 lines or a single STM-4/ OC-12 line. It can perform clock
synthesis and clock recovery for four 155.52 Mbit/s signals or a single 622.08 Mbit/s serial
signal.
The PHAST-12N device provides RS/section and MS/line overhead processing, high order
AU-3/AU-4/AU-4-Xc/STS-1/STS-3c/STC-6c/STS-9c/STS-12c pointer tracking and retiming,
and high order VC-3/VC-4/VC-4-Xc/STS-1/STS-3c/STS-6c/STS-9c/STS-12c SPE path
overhead processing and performance monitoring. It provides full non-blocking cross
connecting at the high order path level allowing path loopbacks, line/MSP protection and
UPSR and SNC/P path protection.
The PHAST-12N device supports the following APS architectures:
The device operates from 1.8V and 3.3V power supplies.
Major interfaces include:
The PHAST-12N software driver, API’s and sample applications have the same architecture
as other TranSwitch device software deliverables and is meant to be easily integrated with
them. The application software calls the driver functions to configure, control and manage the
PHAST-12N device. The device driver insulates the application from the internal details of the
device register usage and provides a higher level of abstraction.
1. STM-4/OC-12 mode: 1+1 or 1:1 APS using two devices connected via the APS port
2. STM-1/OC-3 mode: 1+1, 1:1 or 1:n (n<=3) APS using a single device without APS
3. STM-1/OC-3 mode: 1+1, 1:1 or 1:n (n<=7) APS using two devices connected via the
1. Serial LVPECL line interfaces: single STM-4/OC-12 or four STM-1/OC-3
2. 77.76 MHz telecom bus interface
3. 622.08 Mbit/s serial LVDS APS port interface
4. Line/MS Alarm/Ring port selectable per line interface
5. SOH/TOH byte interface
6. DCC interface
7. High Order Path Alarm/Ring port selectable per SDH/SONET path
8. High Order POH byte interface
9. Motorola/Intel style microprocessor interface for configuration, alarms and perfor-
10. JTAG interface to IEEE 1149.1
11. Various reference clocks, and lead programmed HW configuration controls
port
APS port
mance monitoring
O
VERVIEW
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