TXC-06312BIOG Transwitch Corporation, TXC-06312BIOG Datasheet - Page 131

• Manufacturer Part Number: TXC-06312BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06312BIOG

• Lead Free Status / Rohs Status: Supplier Unconfirmed

1 3 1 o f 2 02
Output_SelectNegativeClockEdge
(see
ParityEven
12.1 DROP BUS INTERFACE
Table
0
0
12.1.1 Drop Bus Parity Selection
(see
80)
The Drop bus consists of the following leads:
J0 and J1 marker pulses are always present on the CBDPJ0J1 lead. A V1 marker pulse will
be present when TUG-2 is mapped in the SDH/SONET stream (see
on page
The Drop bus always outputs all bytes on the bus. The H1/H2 pointer bytes are always
inserted. Other TOH bytes are don’t cares and must be ignored.
The most significant bit (MSB) of the output data is assigned to CBDPD7. The MSB is defined
as the first bit received in a SDH/SONET byte. The bus rate is 77.76 MHz.
The active CBDPCLK clock edge on which the data and timing signals are clocked out can be
selected.
The parity selection for the Drop bus is according to the following table. The calculated parity
is output on the CBDPPAR lead.
Table
0
1
ParityIncludesTiming
• Output data CBDPD(7-0)
• Output parity CBDPPAR
• Output clock CBDPCLK
• Output J0, J1, and optional V1 marker pulses CBDPJ0J1
• Output payload indication CBDPSPE
(see
80)
85). i.e., when lower-order is mapped in the SDH/SONET traffic.
Table
0
1
80)
Output signals are clocked out on positive CBDPCLK clock edge.
Output signals are clocked out on negative CBDPCLK clock edge.
Odd parity is calculated for the data output leads CBDPD(7-0).
Odd parity is calculated for the data and timing output leads,
CBDPD(7-0), CBDPJ0J1 and CBDPSPE.
- Telecom Bus -
Active CBDPCLK clock edge
Drop Bus Parity Selection
12.0 T
PRELIMINARY TXC-06312B-MB, Ed. 2
ELECOM
PHAST-12N Device
“SDH/SONET Mapping”
DATA SHEET
TXC-06312B
B
June 2005
US