MT41J256M8DA-125:H Micron Technology Inc, MT41J256M8DA-125:H Datasheet - Page 199
MT41J256M8DA-125:H
Manufacturer Part Number
MT41J256M8DA-125:H
Description
Manufacturer
Micron Technology Inc
Datasheet
1.MT41J256M8DA-125H.pdf
(210 pages)
Specifications of MT41J256M8DA-125:H
Lead Free Status / Rohs Status
Supplier Unconfirmed
- Current page: 199 of 210
- Download datasheet (13Mb)
ODT Off During READs
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
Because the device cannot terminate and drive at the same time, R
at least one-half clock cycle before the READ preamble by driving the ODT ball LOW (if
either R
amble, as shown in the following example.
Note: ODT may be disabled earlier and enabled later than shown Figure 116 (page 200).
TT,nom
or R
TT(WR)
is enabled). R
199
TT
Micron Technology, Inc. reserves the right to change products or specifications without notice.
may not be enabled until the end of the post-
2Gb: x4, x8, x16 DDR3 SDRAM
© 2006 Micron Technology, Inc. All rights reserved.
TT
must be disabled
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