EVAL-AD5551/52EB Analog Devices Inc, EVAL-AD5551/52EB Datasheet - Page 3

• Manufacturer Part Number: EVAL-AD5551/52EB
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5551/52EB

• Lead Free Status / Rohs Status: Not Compliant

TIMING CHARACTERISTICS
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
Specifications subject to change without notice.
SCLK
Guaranteed by design. Not production tested.
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns (10% to
1
2
3
4
5
6
7
8
9
10
11
12
90% of +3 V and timed from a voltage level of +1.6 V).
LDAC
SCLK
DIN
Limit at T
All Versions
25
40
20
20
15
15
35
20
15
0
30
30
30
CS
AD5552 ONLY. MAY BE TIED PERMANENTLY LOW IF REQUIRED.
t
MIN
12
t
6
, T
DB13
t
1, 2
t
4
8
MAX
(V
otherwise noted.)
t
DD
9
= 5 V
t
2
5%, V
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
REF
t
1
t
= 2.5 V, AGND = DGND = 0 V. All specifications T
3
DB0
t
7
t
t
5
11
t
10
Description
SCLK Cycle Frequency
SCLK Cycle Time
SCLK High Time
SCLK Low Time
CS Low to SCLK High Setup
CS High to SCLK High Setup
SCLK High to CS Low Hold Time
SCLK High to CS High Hold Time
Data Setup Time
Data Hold Time
LDAC Pulsewidth
CS High to LDAC Low Setup
CS High Time Between Active Periods
AD5551/AD5552
A
= T
MIN
to T
MAX
, unless