IDT82V3355TF IDT, Integrated Device Technology Inc, IDT82V3355TF Datasheet - Page 59
IDT82V3355TF
Manufacturer Part Number
IDT82V3355TF
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT82V3355TF.pdf
(135 pages)
Specifications of IDT82V3355TF
Function
Wan PLL
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
TQFP
Pin Count
64
Mounting
Surface Mount
Lead Free Status / Rohs Status
Not Compliant
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6.2.2
INTERRUPT_CNFG - Interrupt Configuration
INTERRUPTS1_STS - Interrupt Status 1
Programming Information
IDT82V3355
Address: 0CH
Type: Read / Write
Default Value: XXXXXX10
Address: 0DH
Type: Read / Write
Default Value: XX1111XX
7 - 2
7 - 6
5 - 4
3 - 2
1 - 0
Bit
Bit
1
0
7
7
-
-
INTERRUPT REGISTERS
INT_POL
INn_CMOS
HZ_EN
INn_DIFF
Name
Name
-
-
-
6
6
-
-
Reserved.
This bit determines the output characteristics of the INT_REQ pin.
0: The output on the INT_REQ pin is high/low when the interrupt is active; the output is the opposite when the interrupt is inactive.
1: The output on the INT_REQ pin is high/low when the interrupt is active; the output is in high impedance state when the interrupt
is inactive. (default)
This bit determines the active level on the INT_REQ pin for an active interrupt indication.
0: Active low. (default)
1: Active high.
Reserved.
This bit indicates the validity changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’) for the corresponding INn_DIFF; i.e.,
whether there is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the corresponding INn_DIFF bit (b5/4, 4AH). Here n is 2 or 1.
0: Has not changed.
1: Has changed. (default)
This bit is cleared by writing a ‘1’.
This bit indicates the validity changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’) for the corresponding INn_CMOS; i.e.,
whether there is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the corresponding INn_CMOS bit (b3/2, 4AH). Here n is 2 or 1.
0: Has not changed.
1: Has changed. (default)
This bit is cleared by writing a ‘1’.
Reserved.
IN2_DIFF
5
-
5
IN1_DIFF
4
-
4
59
IN2_CMOS
3
-
3
Description
Description
IN1_CMOS
2
-
2
SYNCHRONOUS ETHERNET WAN PLL
HZ_EN
1
1
-
INT_POL
May 19, 2009
0
0
-
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