IDT82V3355TF IDT, Integrated Device Technology Inc, IDT82V3355TF Datasheet - Page 83
IDT82V3355TF
Manufacturer Part Number
IDT82V3355TF
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT82V3355TF.pdf
(135 pages)
Specifications of IDT82V3355TF
Function
Wan PLL
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
TQFP
Pin Count
64
Mounting
Surface Mount
Lead Free Status / Rohs Status
Not Compliant
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IN1_IN2_DIFF_STS - Differential Input Clock 1 & 2 Status
Programming Information
IDT82V3355
Address: 45H
Type: Read
Default Value: X110X110
Bit
7
6
5
4
3
2
1
0
7
-
IN2_DIFF_NO_ACTIVITY_ALARM
IN1_DIFF_NO_ACTIVITY_ALARM
IN2_DIFF_FREQ_HARD_ALARM
IN1_DIFF_FREQ_HARD_ALARM
IN2_DIFF_FREQ
_HARD_ALARM
IN2_DIFF_PH_LOCK_ALARM
IN1_DIFF_PH_LOCK_ALARM
6
Name
-
-
CTIVITY_ALARM
IN2_DIFF_NO_A
5
Reserved.
This bit indicates whether IN2_DIFF is in frequency hard alarm status.
0: No frequency hard alarm.
1: In frequency hard alarm status. (default)
This bit indicates whether IN2_DIFF is in no-activity alarm status.
0: No no-activity alarm.
1: In no-activity alarm status. (default)
This bit indicates whether IN2_DIFF is in phase lock alarm status.
0: No phase lock alarm. (default)
1: In phase lock alarm status.
If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the
PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0,
08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised.
Reserved.
This bit indicates whether IN1_DIFF is in frequency hard alarm status.
0: No frequency hard alarm.
1: In frequency hard alarm status. (default)
This bit indicates whether IN1_DIFF is in no-activity alarm status.
0: No no-activity alarm.
1: In no-activity alarm status. (default)
This bit indicates whether IN1_DIFF is in phase lock alarm status.
0: No phase lock alarm. (default)
1: In phase lock alarm status.
If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the
PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0,
08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised.
IN2_DIFF_PH_L
OCK_ALARM
4
83
3
-
IN1_DIFF_FREQ
_HARD_ALARM
Description
2
SYNCHRONOUS ETHERNET WAN PLL
CTIVITY_ALARM
IN1_DIFF_NO_A
1
IN1_DIFF_PH_L
OCK_ALARM
May 19, 2009
0
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