LFEC15E-5FN484C Lattice, LFEC15E-5FN484C Datasheet - Page 11
LFEC15E-5FN484C
Manufacturer Part Number
LFEC15E-5FN484C
Description
FPGA LatticeEC Family 15400 Cells 420MHz 130nm (CMOS) Technology 1.2V 484-Pin FBGA
Manufacturer
Lattice
Datasheet
1.LFEC3E-5TN144C.pdf
(163 pages)
Specifications of LFEC15E-5FN484C
Package
484FBGA
Family Name
LatticeEC
Device Logic Units
15400
Maximum Internal Frequency
420 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
352
Ram Bits
358400
In System Programmability
Yes
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Price
Company:
Part Number:
LFEC15E-5FN484C
Manufacturer:
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Quantity:
40
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LFEC15E-5FN484C
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LATTICE
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10 000
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Manufacturer:
TI
Quantity:
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Lattice Semiconductor
Secondary Clock Sources
LatticeECP/EC devices have four secondary clock resources per quadrant. The secondary clock branches are
tapped at every PFU. These secondary clock networks can also be used for controls and high fanout data. These
secondary clocks are derived from four clock input pads and 16 routing signals as shown in Figure 2-7.
Figure 2-7. Secondary Clock Sources
Clock Routing
The clock routing structure in LatticeECP/EC devices consists of four Primary Clock lines and a Secondary Clock
network per quadrant. The primary clocks are generated from MUXs located in each quadrant. Figure 2-8 shows
this clock routing. The four secondary clocks are generated from MUXs located in each quadrant as shown in
Figure 2-9. Each slice derives its clock from the primary clock lines, secondary clock lines and routing as shown in
Figure 2-10.
From Routing
From Routing
From Routing
From Routing
Routing
Routing
From
From
Routing
Routing
20 Secondary Clock Sources
To Quadrant Clock Selection
From
From
2-8
Routing
Routing
From
From
LatticeECP/EC Family Data Sheet
Routing
Routing
From
From
From Routing
From Routing
From Routing
From Routing
Architecture
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