ADSP-BF527KBCZ-6C2 Analog Devices Inc, ADSP-BF527KBCZ-6C2 Datasheet - Page 10

• Manufacturer Part Number: ADSP-BF527KBCZ-6C2
• Description: IC DSP 16BIT 600MHZ 289CSPBGA
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF527KBCZ-6C2

• Package / Case: 289-CSPBGA
• Interface: DMA, Ethernet, I²C, PPI, SPI, SPORT, UART, USB
• Clock Rate: 600MHz
• Non-volatile Memory: ROM (32 kB)
• On-chip Ram: 132kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.10V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Svhc: No SVHC (18-Jun-2010)
• Cache On Chip L1/l2 Memory: 48KB
• Core Frequency Typ: 600MHz
• Dsp Type: Core
• External Supported Memory: SDRAM, SRAM, FLASH, ROM
• Interface Type: SPI, Parallel, 2 Wire
• Rohs Compliant: Yes
• Mmac: 1200
• No. Of Pins: 289
• Package: 289CSP-BGA
• Maximum Speed: 600 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-BF527-MPSKIT - BOARD EVAL MEDIA PLAYER BF527ADZS-BF527-EZLITE - BOARD EVAL ADSP-BF527
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

USB Mode
In USB mode, the codec supports digital audio sampling rates
from 8 kHz to 96 kHz. USB mode is enabled on the codec
to support the common universal serial bus (USB) clock rate of
Table 2. Sampling Rate Lookup Table, USB Mode (USB Enabled)
1
CODEC_MCLK
(CLKDIV2 = 0)
12.000 MHz
CODEC_BCLK frequency is for master mode and slave right-justified mode only.
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
CODEC_MCLK
(CLKDIV2 = 1)
24.000 MHz
ADC Sampling Rate
(ADCLRC)
8 kHz (CODEC_MCLK/1500)
8 kHz (CODEC_MCLK/1500)
8.0214 kHz (CODEC_MCLK/1496) 8.0214 kHz (CODEC_MCLK/1496) 1
8.0214 kHz (CODEC_MCLK/1496) 44.118 kHz (CODEC_MCLK/272)
11.0259 kHz (CODEC_MCLK/1088) 11.0259 kHz (CODEC_MCLK/1088) 1
12 kHz (CODEC_MCLK/1000)
16 kHz (CODEC_MCLK/750)
22.0588 kHz (CODEC_MCLK/544) 22.0588 kHz (CODEC_MCLK/544) 1
24 kHz (CODEC_MCLK/500)
32 kHz (CODEC_MCLK/375)
44.118 kHz (CODEC_MCLK/272)
44.118 kHz (CODEC_MCLK/272)
48 kHz (CODEC_MCLK/250)
48 kHz (CODEC_MCLK/250)
88.235 kHz (CODEC_MCLK/136)
96 kHz (CODEC_MCLK/125)
Rev. A | Page 10 of 36 | March 2010
DAC Sampling Rate
(DACLRC)
8 kHz (CODEC_MCLK/1500)
48 kHz (CODEC_MCLK/250)
12 kHz (CODEC_MCLK/1000)
16 kHz (CODEC_MCLK/750)
24 kHz (CODEC_MCLK/500)
32 kHz (CODEC_MCLK/375)
8.0214 kHz (CODEC_MCLK/1496) 1
44.118 kHz (CODEC_MCLK/272)
8 kHz (CODEC_MCLK/1500)
48 kHz (CODEC_MCLK/250)
88.235 kHz (CODEC_MCLK/136)
96 kHz (CODEC_MCLK/125)
12 MHz, or to support 24 MHz if the CLKDIV2 control register
bit is activated. The programmer must set the appropriate sam-
pling rate in the SR control bits (Register R8, Bit D2 to Bit D5).
See
Table 2
for sampling rates in USB mode.
USB SR [3:0] BOSR CODEC_BCLK
1
1
1
1
1
1
1
1
1
1
1
1
0011
0010
1011
1010
1100
1000
1010
1101
1110
0110
1001
1000
0001
0000
1111
0111
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
(MS = 1)
CODEC_MCLK
CODEC_MCLK
CODEC_MCLK
CODEC_MCLK
CODEC_MCLK
CODEC_MCLK
CODEC_MCLK
CODEC_MCLK
CODEC_MCLK
CODEC_MCLK
CODEC_MCLK
CODEC_MCLK
CODEC_MCLK
CODEC_MCLK
CODEC_MCLK
CODEC_MCLK
1