AD14060BF-4 Analog Devices Inc, AD14060BF-4 Datasheet - Page 34

• Manufacturer Part Number: AD14060BF-4
• Description: IC DSP CMOS 32BIT 308CQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of AD14060BF-4

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 2MB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 308-CQFP
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Clock Freq (max): 40MHz
• Mips: 40
• Device Input Clock Speed: 40MHz
• Ram Size: 1.9073535156MB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 308
• Package Type: CQFP
• Lead Free Status / Rohs Status: Not Compliant

AD14060/AD14060L
DETAILED DESCRIPTION
ARCHITECTURAL FEATURES
ADSP-21060 Core
The AD14060/AD14060L is based on the powerful
ADSP-21060 (SHARC) DSP chip. The ADSP-21060 SHARC
combines a high performance floating-point DSP core with
integrated, on-chip system features, including a 4-Mbit SRAM
memory, host processor interface, DMA controller, serial ports,
and both link port and parallel bus connectivity for glueless
DSP multiprocessing (see Figure 21). It is fabricated in a high
speed, low power CMOS process, and has a 25 ns instruction
cycle time. The arithmetic/logic unit (ALU), multiplier, and
shifter all perform single-cycle instructions, and the three units
are arranged in parallel, maximizing computational throughput.
The SHARC features an enhanced Harvard architecture, in
which the data memory (DM) bus transfers data and the
program memory (PM) bus transfers both instructions and
data. An on-chip instruction cache selectively caches only those
instructions whose fetches conflict with the PM bus data
accesses. This combines with the separate program and data
memory buses to enable 3-bus operation for fetching an
instruction and two operands, all in a single cycle. The SHARC
also contains a general-purpose data register file, which is a
10-port, 32-register (16 primary, 16 secondary) file. Each
SHARC’s core also implements two data address generators
(DAGs), implementing circular data buffers in hardware. The
DAGs contain sufficient registers to allow the creation of up to
32 circular buffers. The 48-bit instruction word accommodates
a variety of parallel operations for concise programming. For
example, the ADSP-21060 can conditionally execute a multiply,
an add, a subtract, and a branch, all in a single instruction.
The SHARCs contain 4 Mbits of on-chip SRAM each, organized
as two blocks of 2 Mbits, which can be configured for different
combinations of code and data storage. The memory can be
configured as a maximum of 128k words of 32-bit data, 256k
words of 16-bit data, 80k words of 48-bit instructions (or 40-bit
data), or combinations of different word sizes up to 4 Mbits. A
16-bit floating-point storage format is supported, which
effectively doubles the amount of data that can be stored on-
chip. Conversion between the 32-bit floating-point and 16-bit
floating-point formats is done in a single instruction. Each
memory block is dual-ported for single-cycle, independent
access by the core processor and I/O processor or DMA
controller. The dual-ported memory and separate on-chip buses
allow two data transfers from the core and one from the I/O, all
in a single cycle.
Rev. B | Page 34 of 48
SHARED MEMORY MULTIPROCESSING
The AD14060/AD14060L takes advantage of the powerful
multiprocessing features built into the SHARC. The SHARCs
are connected to maximize the performance of this cluster-of-
four architecture, and still allow for off-module expansion. The
AD14060/AD14060L in itself is a complete shared memory
multiprocessing system, as shown in Figure 22. The unified
address space of the SHARCs allows direct interprocessor
accesses of each SHARCs’ internal memory. In other words,
each SHARC can directly access the internal memory and IOP
registers of each of the other SHARCs by simply reading or
writing to the appropriate address in multiprocessor memory
space (see Figure 23)—this is called a direct read or direct write.
Bus arbitration is accomplished with the on-SHARC arbitration
logic. Each SHARC has a unique ID, and drives the bus-request
(BR) line corresponding to its ID, while monitoring all others.
BR 1 to BR 4 are used within the AD14060/AD14060L, while
BR 5 and BR 6 can be used for expansion. All bus requests ( BR 1
to BR 6) are included in the module I/O. Two different priority
schemes, fixed and rotating, are available to resolve competing
bus requests. The RPBA pin selects which scheme is used. When
RPBA is high, rotating priority bus arbitration is selected; when
RPBA is low, fixed priority is selected.
Bus mastership is passed from one SHARC to another during a
bus transition cycle. A bus transition cycle occurs only when the
current bus master de-asserts its BR line and one of the slave
SHARCs asserts its BR line. The bus master can, therefore,
retain bus mastership by keeping its BR line asserted. When the
bus master de-asserts its BR line and no other BR line is
asserted, then the master does not lose any bus cycles. When
more than one SHARC asserts its BR line, the SHARC with the
highest priority request becomes bus master on the following
cycle. Each SHARC observes all the BR lines, and, therefore,
tracks when a bus transition cycle has occurred, and which
processor has become the new bus master. Master processor
changeover incurs only one cycle of overhead. Table 23 shows
an example of a bus transition sequence.
Table 23. Rotating Priority Arbitration Example
Cycle
1
2
3
4
5
1–5 = Assigned priority.
M = Bus mastership (in that cycle).
BR = Requesting bus mastership with BR x.
ID1
M
4
4
5 BR
1 BR
ID2
1
5 BR
5 BR
M
2
Hardware Processor IDs
ID3
2 BR
M-BR
M
1
3
ID4
3
1
1
2
4
ID5
4
2
2
3
5
ID6
5
3
3
4 BR
M
Priority
Initial priority
assignments
Final priority
assignments