EPF6016TC144-3 Altera, EPF6016TC144-3 Datasheet - Page 3
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EPF6016TC144-3
Manufacturer Part Number
EPF6016TC144-3
Description
IC FLEX 6000 FPGA 16K 144-TQFP
Manufacturer
Altera
Series
FLEX 6000r
Datasheet
1.EPF6010ATC100-3N.pdf
(52 pages)
Specifications of EPF6016TC144-3
Number Of Logic Elements/cells
1320
Number Of Labs/clbs
132
Number Of I /o
117
Number Of Gates
16000
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Total Ram Bits
-
Other names
544-1282
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPF6016TC144-3
Manufacturer:
ALTERA
Quantity:
48
Company:
Part Number:
EPF6016TC144-3
Manufacturer:
SANYO
Quantity:
47
Company:
Part Number:
EPF6016TC144-3
Manufacturer:
ALTERA
Quantity:
1 066
Part Number:
EPF6016TC144-3
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EPF6016TC144-3N
Manufacturer:
ALTERA42
Quantity:
1 341
Part Number:
EPF6016TC144-3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
General
Description
Note:
(1)
Altera Corporation
Table 3. FLEX 6000 Device Performance for Common Designs
16-bit loadable counter
16-bit accumulator
24-bit accumulator
16-to-1 multiplexer (pin-to-pin)
16 × 16 multiplier with a 4-stage pipeline
This performance value is measured as a pin-to-pin delay.
Application
The Altera
a low-cost alternative to high-volume gate array designs. FLEX 6000
devices are based on the OptiFLEX architecture, which minimizes die size
while maintaining high performance and routability. The devices have
reconfigurable SRAM elements, which give designers the flexibility to
quickly change their designs during prototyping and design testing.
Designers can also change functionality during operation via in-circuit
reconfiguration.
FLEX 6000 devices are reprogrammable, and they are 100% tested prior to
shipment. As a result, designers are not required to generate test vectors
for fault coverage purposes, allowing them to focus on simulation and
design verification. In addition, the designer does not need to manage
inventories of different gate array designs. FLEX 6000 devices are
configured on the board for the specific functionality required.
Table 3
performance values shown were obtained using Synopsys DesignWare or
LPM functions. Special design techniques are not required to implement
the applications; the designer simply infers or instantiates a function in a
Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or
schematic design file.
(1)
shows FLEX 6000 performance for some common designs. All
®
FLEX 6000 programmable logic device (PLD) family provides
LEs Used
FLEX 6000 Programmable Logic Device Family Data Sheet
592
16
16
24
10
-1 Speed
Grade
12.1
172
172
136
84
Performance
-2 Speed
Grade
13.4
153
153
123
67
-3 Speed
Grade
16.6
133
108
133
58
Units
MHz
MHz
MHz
MHz
ns
3