EP2C8Q208C7N Altera, EP2C8Q208C7N Datasheet - Page 101
![IC CYCLONE II FPGA 8K 208-PQFP](/photos/6/70/67062/544-208-pqfp_sml.jpg)
EP2C8Q208C7N
Manufacturer Part Number
EP2C8Q208C7N
Description
IC CYCLONE II FPGA 8K 208-PQFP
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C8Q208C7N
Number Of Logic Elements/cells
8256
Number Of Labs/clbs
516
Total Ram Bits
165888
Number Of I /o
138
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Family Name
Cyclone® II
Number Of Logic Blocks/elements
8256
# I/os (max)
138
Frequency (max)
402.58MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
8256
Ram Bits
165888
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1672
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C8Q208C7N
Manufacturer:
ALTERA
Quantity:
8
Part Number:
EP2C8Q208C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
DC
Characteristics
for Different Pin
Types
Altera Corporation
February 2008
Notes to
(1)
(2)
(3)
(4)
Differential 1.8-V
HSTL class I
and II
Differential
SSTL-2 class I
(4)
Differential
SSTL-2 class II
(4)
Differential
SSTL-18 class I
(4)
Differential
SSTL-18 class II
(4)
Table 5–9. DC Characteristics for User I/O Pins Using Differential I/O Standards
I/O Standard
The LVPECL I/O standard is only supported on clock input pins. This I/O standard is not supported on output
pins.
The RSDS and mini-LVDS I/O standards are only supported on output pins.
The differential 1.8-V HSTL and differential 1.5-V HSTL I/O standards are only supported on clock input pins and
PLL output clock pins.
The differential SSTL-18 and SSTL-2 I/O standards are only supported on clock input pins and PLL output clock
pins.
(3)
Table
5–9:
Min
—
—
—
—
—
V
OD
Typ
—
—
—
—
—
(mV)
Table 5–10
I/O pins using single-ended I/O standards
I/O pins using differential I/O standards
Dedicated clock pins
JTAG
Configuration pins
Table 5–10. Bus Hold Support
Max
—
—
—
—
—
ΔV
shows the types of pins that support bus hold circuitry.
Min Max
—
—
—
—
—
OD
Pin Type
(mV)
—
—
—
—
—
V
V
0.125
0.125
0.5 ×
0.5 ×
Min
C C I O
C C I O
—
—
—
–
–
DC Characteristics and Timing Specifications
V
V
V
OCM
0.5 ×
0.5 ×
Typ
C C I O
C C I O
—
—
—
(V)
Cyclone II Device Handbook, Volume 1
V
V
0.125
0.125
0.5 ×
0.5 ×
Max
C C I O
C C I O
—
—
—
+
+
V
V
– 0.28
V
V
V
0.475
– 0.4
0.57
0.76
Min
C C I O
C C I O
T T
T T
T T
V
Note (1)
OH
+
+
+
(V)
Bus Hold
Max
—
—
—
—
—
Yes
No
No
No
No
(Part 2 of 2)
Min
—
—
—
—
—
V
OL
(V)
V
V
V
0.475
Max
0.57
0.76
0.28
0.4
T T
T T
T T
5–11
–
–
–