EP2C8Q208C7N Altera, EP2C8Q208C7N Datasheet - Page 23
![IC CYCLONE II FPGA 8K 208-PQFP](/photos/6/70/67062/544-208-pqfp_sml.jpg)
EP2C8Q208C7N
Manufacturer Part Number
EP2C8Q208C7N
Description
IC CYCLONE II FPGA 8K 208-PQFP
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C8Q208C7N
Number Of Logic Elements/cells
8256
Number Of Labs/clbs
516
Total Ram Bits
165888
Number Of I /o
138
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Family Name
Cyclone® II
Number Of Logic Blocks/elements
8256
# I/os (max)
138
Frequency (max)
402.58MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
8256
Ram Bits
165888
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1672
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C8Q208C7N
Manufacturer:
ALTERA
Quantity:
8
Part Number:
EP2C8Q208C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Figure 2–8. R4 Interconnect Connections
Notes to
(1)
(2)
Altera Corporation
February 2007
C4 interconnects can drive R4 interconnects.
This pattern is repeated for every LAB in the LAB row.
Figure
2–8:
R4 Interconnect
Driving Left
The direct link interconnect allows an LAB, M4K memory block, or
embedded multiplier block to drive into the local interconnect of its left
and right neighbors. Only one side of a PLL block interfaces with direct
link and row interconnects. The direct link interconnect provides fast
communication between adjacent LABs and/or blocks without using
row interconnect resources.
The R4 interconnects span four LABs, three LABs and one M4K memory
block, or three LABs and one embedded multiplier to the right or left of a
source LAB. These resources are used for fast row connections in a four-
LAB region. Every LAB has its own set of R4 interconnects to drive either
left or right.
R4 interconnects can drive and be driven by LABs, M4K memory blocks,
embedded multipliers, PLLs, and row IOEs. For LAB interfacing, a
primary LAB or LAB neighbor (see
interconnect. For R4 interconnects that drive to the right, the primary
LAB and right neighbor can drive on to the interconnect. For R4
interconnects that drive to the left, the primary LAB and its left neighbor
can drive on to the interconnect. R4 interconnects can drive other R4
interconnects to extend the range of LABs they can drive. Additionally,
R4 interconnects can drive R24 interconnects, C4, and C16 interconnects
for connections from one row to another.
Adjacent LAB can
Drive onto Another
LAB's R4 Interconnect
Neighbor
LAB
Figure 2–8
Primary
LAB (2)
shows R4 interconnect connections from an LAB.
C4 Column Interconnects (1)
Neighbor
LAB
Cyclone II Device Handbook, Volume 1
Figure
2–8) can drive a given R4
R4 Interconnect
Driving Right
Cyclone II Architecture
2–11