EP2C8F256C8 Altera, EP2C8F256C8 Datasheet - Page 16
![IC CYCLONE II FPGA 8K 256-FBGA](/photos/6/70/67063/544-256-fbga_sml.jpg)
EP2C8F256C8
Manufacturer Part Number
EP2C8F256C8
Description
IC CYCLONE II FPGA 8K 256-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C8F256C8
Number Of Logic Elements/cells
8256
Number Of Labs/clbs
516
Total Ram Bits
165888
Number Of I /o
182
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-FBGA
Family Name
Cyclone® II
Number Of Logic Blocks/elements
8256
# I/os (max)
182
Frequency (max)
402.58MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
8256
Ram Bits
165888
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1454
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Logic Elements
2–4
Cyclone II Device Handbook, Volume 1
Another special packing mode allows the register output to feed back into
the LUT of the same LE so that the register is packed with its own fan-out
LUT, providing another mechanism for improved fitting. The LE can also
drive out registered and unregistered versions of the LUT output.
In addition to the three general routing outputs, the LEs within an LAB
have register chain outputs. Register chain outputs allow registers within
the same LAB to cascade together. The register chain output allows an
LAB to use LUTs for a single combinational function and the registers to
be used for an unrelated shift register implementation. These resources
speed up connections between LABs while saving local interconnect
resources. See
information on register chain connections.
LE Operating Modes
The Cyclone II LE operates in one of the following modes:
■
■
Each mode uses LE resources differently. In each mode, six available
inputs to the LE—the four data inputs from the LAB local interconnect,
the LAB carry-in from the previous carry-chain LAB, and the register
chain connection—are directed to different destinations to implement the
desired logic function. LAB-wide signals provide clock, asynchronous
clear, synchronous clear, synchronous load, and clock enable control for
the register. These LAB-wide signals are available in all LE modes.
The Quartus
such as library of parameterized modules (LPM) functions, automatically
chooses the appropriate mode for common functions such as counters,
adders, subtractors, and arithmetic functions. If required, you can also
create special-purpose functions that specify which LE operating mode to
use for optimal performance.
Normal Mode
The normal mode is suitable for general logic applications and
combinational functions. In normal mode, four data inputs from the LAB
local interconnect are inputs to a four-input LUT (see
Quartus II Compiler automatically selects the carry-in or the data3
signal as one of the inputs to the LUT. LEs in normal mode support
packed registers and register feedback.
Normal mode
Arithmetic mode
®
II software, in conjunction with parameterized functions
“MultiTrack Interconnect” on page 2–10
Figure
Altera Corporation
for more
February 2007
2–3). The