EP2C35F484C8N Altera, EP2C35F484C8N Datasheet - Page 52
![IC CYCLONE II FPGA 35K 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP2C35F484C8N
Manufacturer Part Number
EP2C35F484C8N
Description
IC CYCLONE II FPGA 35K 484-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C35F484C8N
Number Of Logic Elements/cells
33216
Number Of Labs/clbs
2076
Total Ram Bits
483840
Number Of I /o
322
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone® II
Number Of Logic Blocks/elements
33216
# I/os (max)
322
Frequency (max)
402.58MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
33216
Ram Bits
483840
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
2076
Family Type
Cyclone II
No. Of I/o's
322
I/o Supply Voltage
3.3V
Operating Frequency Max
320MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
P0301 - DE2 CALL FOR ACADEMIC PRICING544-1733 - PCI KIT W/CYCLONE II EP2C35N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1366
EP2C35F484C8N
EP2C35F484C8N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C35F484C8N
Manufacturer:
ALTERA
Quantity:
319
Part Number:
EP2C35F484C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
I/O Structure & Features
Figure 2–22. Column I/O Block Connection to the Interconnect
Notes to
(1)
(2)
2–40
Cyclone II Device Handbook, Volume 1
The 28 data and control signals consist of four data out lines, io_dataout[3..0], four output enables,
io_coe[3..0], four input clock enables, io_cce_in[3..0], four output clock enables, io_cce_out[3..0],
four clocks, io_cclk[3..0], four asynchronous clear signals, io_caclr[3..0], and four synchronous clear
signals, io_csclr[3..0].
Each of the four IOEs in the column I/O block can have two io_datain (combinational or registered) inputs.
Local Interconnect
R4 & R24 Interconnects
Figure
from Logic Array (1)
I/O Block
Control Signals
2–22:
28 Data &
LAB Local
Interconnect
LAB
28
C4 & C24 Interconnects
io_datain0[3..0]
io_datain1[3..0] (2)
Column I/O Block
LAB
LAB
Altera Corporation
Column I/O
Block Contains
up to Four IOEs
io_clk[5..0]
February 2007