EP3SL150F780C4N Altera, EP3SL150F780C4N Datasheet

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... Innovation Drive San Jose, CA 95134 www.altera.com Stratix III Device Handbook, Software Version: Document Version: Document Date: Volume 2 10.0 2.3 © July 2010 ...

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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation ...

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... About–vii How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–vii Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–vii Chapter I. DC & ...

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... EP3SL340 Clock Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–318 EP3SE50 Clock Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–319 EP3SE80 Clock Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–321 EP3SE110 Clock Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–322 EP3SE260 Clock Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–324 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–326 Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–330 Stratix III Device Handbook, Volume 2 Contents © July 2010 Altera Corporation ...

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... The chapter in this book was revised on the following date. Where chapters or groups of chapters are available separately, part numbers are listed. Chapter 1 Stratix III Device Datasheet: DC and Switching Characteristics Revised: Part Number: SIII52001-2.3 © July 2010 Altera Corporation July 2010 Chapter Revision Dates Stratix III Device Handbook, Volume 2 ...

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... Stratix III Device Handbook, Volume 2 © July 2010 Altera Corporation ...

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... Technical training Product literature Non-technical support (General) (Software Licensing) Note: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions The following table shows the typographic conventions that this document uses. Visual Cue Bold Type with Initial Capital ...

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... A warning calls attention to a condition or possible situation that can cause injury to the user. The angled arrow indicates you should press the Enter key. The feet direct you to more information on a particular topic. Typographic Conventions , , data1 tdi , e.g resetn . Also, sections of an actual ) are shown in Courier. TRI © July 2010 Altera Corporation ...

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... Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook. © July 2010 Altera Corporation Section I. DC & Switching III devices are implemented in a system, they are rated according to a ...

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... I–2 Book Title Cross-Referenced from Title Page Section 1: DC & Switching Characteristics of Stratix III Devices © July 2010 Altera Corporation Revision History ...

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... Configuration pins power supply CCPGM V I/O pre-driver power supply CCPD V I/O power supply CCIO © July 2010 Altera Corporation 1. Stratix III Device Datasheet: DC and Switching Characteristics III devices. Electrical characteristics include operating conditions ® may cause permanent damage to the device. Additionally, device (Note 1) (Part ...

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... V 3.0 V ΔT T Figure 1–1, the overshoot voltage is shown in red and is Table 1–2, for an overshoot 4.1 Electrical Characteristics Maximum Unit -0.5 3.75 V -0.5 3.75 V -0.5 4.0 V -55 125 °C - -65 150 °C Table 1–2 and Figure 1–1 © July 2010 Altera Corporation ...

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... V I/O registers power supply CC V PLL digital power supply CCD_PLL V PLL analog power supply CCA_PLL Power supply for the programmable power V CCPT technology © July 2010 Altera Corporation Parameter Condition 4 4.05 4.1 4.15 4.2 4.25 4.3 4.35 4.4 AC Input Voltage (1) 4 ...

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... CCPD (2) For the EP3SL340, EP3SE260, and EP3SL200 devices in the I4L ordering code, the industrial junction temperature range is from 0° 100° C, regardless of supply voltage. (3) Altera recommends a 3.0-V nominal battery voltage when connecting V security key, you may connect the V CCBAT Stratix III Device Handbook, Volume 2 ...

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... Low sustaining V > SUSL current (maximum) High sustaining V < SUSH current (minimum) Low overdrive I 0V < V < V ODL IN current © July 2010 Altera Corporation and V CC_CLKIN Parameter V current specifications CC_CLKIN V current specifications CCPGM Parameter Conditions CCIOMAX CCIOMAX V 1.2 V 1.5 V 1.8 V Min ...

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... Stratix III OCT (Note 1) Calibration Accuracy C3, C4 ±8 ±8 ±8 ±8 ±8 ±8 ±10 ±10 ±10 ±10 ±10 ±10 ±10 ±10 ±10 (4) 1–8. © July 2010 Altera Corporation Unit µA V Unit % % % % % ...

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... V (5) dR/dT is the percentage change of R (6) dR/dV is the percentage change of R © July 2010 Altera Corporation Table 1–7 is valid at the time of calibration. If the voltage or Conditions ...

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... Typical 3 0.029 %/mV 2.5 0.036 %/mV 1.8 0.065 %/mV 1.5 0.104 %/mV 1.2 0.177 %/mV 3 0.294 %/°C 2.5 0.301 %/°C 1.8 0.355 %/°C 1.5 0.344 %/°C 1.2 0.348 %/°C Typical Unit Maximum 300  ( dv/dt, in which C is I/O pin IOPIN © July 2010 Altera Corporation ...

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... LVTTL/ 1.425 1.5 1.575 LVCMOS 1.2-V LVTTL / 1.14 1.2 1.26 LVCMOS 3.0-V PCI 2.85 3 3.15 3.0-V PCI-X 2.85 3 3.15 © July 2010 Altera Corporation Parameter Conditions V = 3.3 V ± 5% CCIO V = 3.0 V ± 5% CCIO V = 2.5 V ± 5% CCIO V = 1.8 V ± 5% CCIO V = 1.5 V ± 5% CCIO V = 1.2 V ± ...

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... VTT - VTT + 6.7 0.475 0.475 0.28 13.4 -13 0.28 CCIO CCIO CCIO CCIO CCIO 0 0.4 CCIO 0 0.4 CCIO 0 0.4 CCIO 0 0.4 CCIO 8 0.25 CCIO CCIO © July 2010 Altera Corporation CCIO I OH (mA) -8.1 -6.7 -8 -16 -8 -16 -8 -16 -8 ...

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... Table 1–18. Differential I/O Standard Specifications (Part (V) I/O CCIO Standard Min Typ Max Min 2.375 2.5 2.625 0.1 2.5 V LVDS (Row I/O) 2.375 2.5 2.625 0.1 © July 2010 Altera Corporation (Note 1) V (V) V (V) V (V) IH(DC) IL(AC) IH(AC) Max Max Min V + 0.15 V -0. 0.15 ...

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... The receiver voltage input range for the data rate when D The receiver voltage input range for the data rate when D Power Consumption Altera offers two ways to estimate power for a design: the Excel-based Early Power Estimator (EPE) and the Quartus The interactive Excel-based Early Power Estimator is typically used prior to designing the FPGA in order to get a magnitude estimate of the device power ...

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... C), except for EP3SL340, EP3SE260, and EP3SL200 devices in the I4L ordering code, where the industrial junction temperature range is from 0° 100° C, regardless of supply voltage. Refer to the figure in “PLL Specifications” in © July 2010 Altera Corporation C2 C3 ...

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Table 1–20. PLL Specifications for Stratix III Devices (Part Symbol Parameter f Input clock frequency IN f Input frequency to the PFD INPFD f PLL VCO operating range VCO Input clock or external feedback t EINDUTY clock ...

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Table 1–20. PLL Specifications for Stratix III Devices (Part Symbol Parameter PLL closed-loop low bandwidth PLL closed-loop medium f bandwidth CLBW PLL closed-loop high bandwidth (6) t Accuracy of PLL phase shift PLL_PSERR Minimum pulse width on ...

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Table 1–20. PLL Specifications for Stratix III Devices (Part Symbol Parameter Cycle to Cycle Jitter for clock output on regular IO 100 MHz) (F OUT t (5), (8) OUTCCJ_IO Cycle to Cycle Jitter for clock output on ...

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... Maximum for loopback input registers disabled, Round and Saturation disabled, pipeline and output registers enabled. (5) The F for the EP3SL200, EP3SE260, and EP3SL340 devices at the C2 speed grade is 7% slower than the C2 values shown in the table. max © July 2010 Altera Corporation (Note 1) C2 (5) ...

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... July 2010 Altera Corporation Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz ...

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... ROM 2 Port (3), (5) Single-port 16K × × 18 Single-port 4K × 36 True dual-port 16K × × 18 × 36 with read-during-write option set to Old Data Simple dual-port 16K × × 18, 4K × 36 × 72 with read-during-write option set to Old Data © July 2010 Altera Corporation C2 ( TriMatrix ALUTs ...

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... Unit max 100 MHz 100 MHz 40 MHz Remote value in Fast Active Serial configuration, refer to for the Min Max Unit 30 — — — — — — ns — — — © July 2010 Altera Corporation I4L Unit V = CCL 0.9 V 120 MHz 1800 ps 1100 ps ...

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... HSDR DDR Register SERDES factor Uses SDR (4) Register SERDES factor LVDS_E_3R -f HSDR (4) (data rate © July 2010 Altera Corporation 1–25. General-purpose I/O standards such as 3.3, for the definitions of the high-speed timing (Note 1), (2) C2 C3, I3 — 800 5 — 717 5 — ...

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... July 2010 Altera Corporation Mbps Mbps Mbps Mbps Mbps UI ± PPM ...

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... Table 1–26. DPA Lock Time Specifications for Stratix III Devices Number of Data Transitions Training Standard in one Pattern Repetition of Training Pattern 0000000000 SPI-4 2 1111111111 00001111 2 Parallel Rapid I/O 10010000 4 © July 2010 Altera Corporation (Note 1), (2) C2 C3, I3 — 300 — — 300 — (Note 1), (2), (3) (Part Number of repetitions per 256 Condition (5) ...

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... The DPA lock time stated in this table applies to both commercial and industrial grade. (4) These are the number of repetitions for the stated training pattern to achieve 256 data transitions. (5) Altera recommends PLL re-calibration for the situations below to guarantee DPA locking: ■ Sparse data transitions. For example: Repeating sequences of ten 1s and ten 0s. ...

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... Use these specifications to determine timing margins for source synchronous paths between the Stratix III FPGA and the external memory device. For more information, refer to the figure for “SW (sampling window)” in the on page 1–326. © July 2010 Altera Corporation 10,000 17,565 1,493,000 50,000,000 of the External Memory Interfaces Handbook. Table 1– ...

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... External Memory © July 2010 Altera Corporation Hold 311 — 311 326 276 261 291 350 291 350 356 356 ...

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... DQS SSTL DDR2 SDRAM 1.8-V Single-ended DQS SSTL DDR SDRAM 2.5-V Single-ended DQS SSTL 1.5-V QDRII/II+ SRAM HSTL QDRII/II+ SRAM 1.5-V Emulation (2) HSTL © July 2010 Altera Corporation (Note 1) (Part C3 1 1.1 V CCL CCL Width TCCS (ps) TCCS (ps) Lead Lag Lead Lag × ...

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... External Memory Number of DQS Delay Delay Chains Buffer Mode 16 Low 12 Low 10 Low 8 Low 12 High 10 High 8 High 6 High © July 2010 Altera Corporation C4L, I4L V = 0.9 V CCL TCCS (ps) Lag 380 518 400 538 415 521 380 518 (1) ...

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... The clock jitter specification applies to memory output clock pins generated using differential signal-splitter and DDIO circuits clocked by a PLL output routed on a regional or global clock network as specified. Altera recommends using the regional clock networks whenever possible. © July 2010 Altera Corporation ...

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... Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Description C2 Symbol Min Max 45 55 I/O Timing Min Typical Max Unit — — 20 MHz — 1000 — cycles — 28 — cycles — 2.5 — ns (Note Unit Min Max Min Max © July 2010 Altera Corporation ...

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... EP3SL200 EP3SL340 EP3SE50 EP3SE80 EP3SE110 EP3SE260 I/O Timing Measurement Methodology Altera characterizes timing delays at the worst-case process, minimum voltage, and maximum temperature for input register setup time (t Quartus II software uses the following equations to calculate t Stratix III devices input signals data delay from the input pin to the input register ...

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... Figure 1–4. Input Register Setup and Hold Timing Diagram For output timing, different I/O standards require different baseline loading techniques for reporting timing delays. Altera characterizes timing delays with the required termination for each I/O standard and with 0 pF (except for PCI and PCI-X, which use 10 pF) loading ...

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... Figure 1–7. Output Delay Timing Report Setup for Differential Outputs with Single External Resistor Figure 1–8. Output Delay Timing Report Setup for Differential Outputs with Three External Resistor © July 2010 Altera Corporation 1–7. Figure 1–6 shows the circuit that is represented by ...

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... July 2010 Altera Corporation ...

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... HSTL CLASS I 1.2-V Differential — — HSTL CLASS II LVDS — 100 MINI-LVDS — 100 RSDS — 100 LVDS_E_1R — 100 LVDS_E_3R 120 100 © July 2010 Altera Corporation Loading and Termination CCIO CCPD CC 25 — 1.375 2.325 1.02 50 — 1.09 2.325 1 ...

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... V). CC and V . CCIO CCPD I/O Standard I/O Timing Measurement Point V C (pF MEAS — 0 1.1625 — 0 1.1625 — 0 1.1625 — 0 1.1625 Capacitive Unit Load © July 2010 Altera Corporation ...

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... You can set the parameter values in the Quartus II software by selecting D1, D2, D3, D4, D5, and D6 in the Assignment Name column. (2) The minimum offset represented in this table does not include the intrinsic delay. © July 2010 Altera Corporation I/O Standard Stratix III Device I/O Features ...

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... V 1.1 V 1.1 V 0.9 V 1.830 1.304 1.531 1.475 1.830 2.471 1.947 2.232 2.148 2.471 1.830 1.304 1.531 1.475 1.830 2.471 1.947 2.232 2.148 2.471 1.829 1.306 1.530 1.474 1.829 2.470 1.949 2.231 2.147 2.470 © July 2010 Altera Corporation Units V = CCL ...

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... GCLK su PLL t 1.159 h t -0.619 su GCLK t 0.747 SSTL-18 h CLASS II t -0.906 GCLK su PLL t 1.159 h © July 2010 Altera Corporation CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V -0.700 -1.003 -1.105 -1.310 -1.265 -1.626 -1.105 -1.310 -1.265 -1.626 0.825 1.181 1.306 1 ...

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... July 2010 Altera Corporation Units = CCL ...

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... V t -0.870 GCLK su PLL t 1.000 h t 0.984 su GCLK t -0.821 h 1 0.973 GCLK su PLL t 0.935 h © July 2010 Altera Corporation CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V -0.914 -1.291 -1.412 -1.634 -1.580 -1.842 -1.428 -1.639 -1.588 -1.875 1.040 1.554 1.774 1.924 1.808 ...

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... July 2010 Altera Corporation Units = CCL ...

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... GCLK su PLL t 1.003 h t 0.904 su GCLK t -0.655 3.0-V h PCI-X t -0.890 GCLK su PLL t 1.003 h © July 2010 Altera Corporation CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V 0.906 1.473 -1.503 -1.682 -1.598 -1.620 -1.497 -1.674 -1.587 -1.665 -0.645 1.473 -1.311 -1.418 -1.362 -1.630 -1.322 -1.428 -1.374 -1.666 -0 ...

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... I/O Timing I3 I4 I4L Units CCL CCL CCL CCL CCL 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation ...

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... PLL 2.5 V GCLK 3.024 t co 12mA GCLK 3.380 t co PLL GCLK 2.986 t co 16mA GCLK 3.342 t co PLL © July 2010 Altera Corporation C4L CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V 3.034 4.253 4.610 5.075 4.958 5.157 4.610 5.075 4.958 5.157 3 ...

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... I/O Timing I3 I4 I4L Units CCL CCL CCL CCL CCL 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation ...

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... PLL GCLK 2.994 t co 10mA GCLK 3.350 t co PLL GCLK 2.994 t co 12mA GCLK 3.350 t co PLL © July 2010 Altera Corporation C4L CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V 3.209 4.636 5.065 5.608 5.490 5.692 5.065 5.608 5.490 5.692 3 ...

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... I/O Timing I3 I4 I4L Units CCL CCL CCL CCL CCL 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation ...

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... GCLK 2.998 t co 12mA GCLK 3.354 t co PLL GCLK 2.996 t 1.5-V co HSTL 16mA GCLK 3.352 t CLASS II co PLL © July 2010 Altera Corporation C4L CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V 2.995 4.233 4.598 5.069 4.951 5.153 4.598 5.069 4.951 5.153 3 ...

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... I/O Timing I3 I4 I4L Units CCL CCL CCL CCL CCL 0.9 V 1.1 V 1.1 V 1 © July 2010 Altera Corporation ...

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... PLL 3.067 GCLK t 2 8mA GCLK 1.383 t co PLL 3.021 GCLK t co 12mA GCLK 1.326 t co PLL © July 2010 Altera Corporation C4L CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V 3.438 4.781 5.176 5.684 5.549 5.751 5.305 5.818 5.682 5.828 1 ...

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... I/O Timing I3 I4 I4L Units CCL CCL CCL CCL CCL 0.9 V 1.1 V 1.1 V 1 © July 2010 Altera Corporation ...

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... PLL SSTL-15 3.036 GCLK t co CLASS I 6mA GCLK 1.305 t co PLL 3.025 GCLK t co 8mA GCLK 1.294 t co PLL © July 2010 Altera Corporation C4L CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V 3.271 4.617 5.015 5.525 5.389 5.596 5.141 5.653 5.518 5.664 1 ...

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... I/O Timing I3 I4 I4L Units CCL CCL CCL CCL CCL 0.9 V 1.1 V 1.1 V 1 © July 2010 Altera Corporation ...

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... GCLK DIFFERENTIAL 0.822 t h 1.8-V HSTL 1.135 t GCLK CLASS I su PLL -0.884 t h © July 2010 Altera Corporation Table 1–48 list the maximum I/O timing parameters for EP3SL50 Commercial CCL CCL CCL CCL 1.1 V 1.1 V 1 ...

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... July 2010 Altera Corporation Units = ...

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... PLL -0.818 t h -0.757 t su GCLK DIFFERENTIAL 0.873 t h 1.8-V 1.054 t HSTL CLASS I GCLK su PLL -0.804 t h © July 2010 Altera Corporation Commercial CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V -0.939 -0.988 -0.952 -1.089 -1.040 -1.316 -0.916 -1.048 -1.000 -1.349 1 ...

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... July 2010 Altera Corporation Units = ...

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... GCLK 3.031 t co PLL 3.031 GCLK t DIFFERENTIAL co 1.2-V HSTL 16mA GCLK 3.035 t CLASS II co PLL © July 2010 Altera Corporation Fast Model CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.246 4.575 4.976 5.487 5.347 5.565 5.101 5.612 5.474 5.631 3.249 4.622 5.031 5.549 5.409 5.627 5.160 5.678 5.540 5.697 3 ...

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... I/O Timing C4L I3 I4 I4L CCL CCL CCL CCL CCL CCL 1.1 V 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation Units = ...

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... DIFFERENTIAL GCLK 3.064 t 1.8-V SSTL co PLL CLASS II GCLK 3.053 t co 16mA GCLK 3.048 t co PLL © July 2010 Altera Corporation Fast Model CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.279 4.646 5.054 5.571 5.431 5.649 5.181 5.698 5.560 5.717 3.269 4.636 5.043 5.561 5.421 5.639 5.170 5.688 5.550 5.707 3 ...

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... I/O Timing C4L I3 I4 I4L CCL CCL CCL CCL CCL CCL 1.1 V 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V C4L I3 I4 I4L CCL CCL CCL CCL CCL 1.1 V 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation Units = Units = CCL ...

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... GCLK 2.668 t HSTL CLASS I co PLL GCLK 3.062 t DIFFERENTIAL co 1.8-V 12mA GCLK 3.044 t HSTL CLASS I co PLL © July 2010 Altera Corporation Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.315 4.710 5.123 5.649 5.505 5.704 5.258 5.787 5.643 5.772 3 ...

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... I/O Timing C4L I3 I4 I4L CCL CCL CCL CCL CCL 1.1 V 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation Units = CCL ...

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... Table 1–50. EP3SL50 Row Pin Delay Adders for Regional Clock Fast Model Parameter Industrial Commercial RCLK input adder 0.111 0.124 RCLK PLL input adder 0.101 0.107 RCLK output adder -0.113 -0.127 RCLK PLL output adder -0.107 -0.113 © July 2010 Altera Corporation Fast Model Commercial CCL CCL CCL 1 ...

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... July 2010 Altera Corporation Units = CCL ...

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... GCLK su PLL t 1.149 h t -0.732 su GCLK t 0.856 1.5-V HSTL h CLASS II t -0.885 GCLK su PLL t 1.138 h © July 2010 Altera Corporation CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V -0.748 -1.074 -1.164 -1.104 -1.058 -1.437 -1.164 -1.104 -1.058 -1.437 0.873 1.247 1.360 1 ...

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... July 2010 Altera Corporation Units = Units = ...

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... GCLK su PLL t 0.950 h t -0.850 su GCLK t 1.010 SSTL-18 h CLASS II t 0.964 GCLK su PLL t -0.850 h © July 2010 Altera Corporation CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V -0.847 1.377 1.519 1.765 1.697 0.973 -1.191 -1.310 -1.531 -1.478 -1.750 -1.314 -1.528 -1.479 -1.778 ...

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... July 2010 Altera Corporation Units = ...

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... LVTTL GCLK 3.005 t co 12mA GCLK 3.331 t co PLL GCLK 2.986 t co 16mA GCLK 3.313 t co PLL © July 2010 Altera Corporation CCL CCL CCL CCL Commercial 1.1 V 1.1 V 1.1 V 1.1 V 3.187 4.411 4.765 5.226 5.105 5.313 4.765 5.226 5.105 5.313 3 ...

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... I/O Timing C4L I3 I4 I4L = CCL CCL CCL CCL CCL 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation Units ...

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... PLL GCLK 3.021 t co 10mA GCLK 3.348 t co PLL GCLK 3.015 t co 12mA GCLK 3.343 t co PLL © July 2010 Altera Corporation Commercial CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V 3.378 4.810 5.219 5.742 5.621 5.829 5.219 5.742 5.621 5.829 3 ...

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... I/O Timing C4L I3 I4 I4L = CCL CCL CCL CCL CCL 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation Units ...

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... GCLK 3.343 t co PLL SSTL-15 CLASS II GCLK 3.019 t co 16mA GCLK 3.346 t co PLL © July 2010 Altera Corporation Commercial CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V 3.020 4.262 4.621 5.087 4.966 5.174 4.621 5.087 4.966 5.174 3 ...

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... I/O Timing C4L I3 I4 I4L = CCL CCL CCL CCL CCL 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation Units ...

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... PCI — GCLK 3.467 t co PLL GCLK 3.140 t co 3.0-V — GCLK PCI-X 3.467 t co PLL © July 2010 Altera Corporation Commercial CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V 3.035 4.284 4.647 5.117 4.996 5.204 4.647 5.117 4.996 5.204 3 ...

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... I/O Timing C4L I3 I4 I4L CCL CCL CCL CCL CCL 1.1 V 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation Units = CCL ...

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... GCLK 1.318 t co PLL 2.963 GCLK t co SSTL-2 16mA GCLK CLASS II 1.309 t co PLL © July 2010 Altera Corporation Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.691 5.275 5.573 6.134 5.998 6.210 5.723 6.286 6.151 6.297 1.915 2 ...

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... I/O Timing C4L I3 I4 I4L CCL CCL CCL CCL CCL 1.1 V 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation Units = CCL ...

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... PCI — GCLK 1.429 t co PLL 3.076 GCLK t co 3.0-V — GCLK PCI-X 1.429 t co PLL © July 2010 Altera Corporation Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.241 4.580 4.964 5.472 5.336 5.548 5.097 5.606 5.471 5.617 1 ...

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... July 2010 Altera Corporation Units = ...

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... GCLK DIFFERENTIAL 0.822 t h 2.5-V SSTL 1.135 t GCLK CLASS II su PLL -0.884 t h © July 2010 Altera Corporation Commercial CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V -0.740 -1.091 -1.204 -1.329 -1.272 -1.559 -1.205 -1.329 -1.275 -1.595 ...

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... July 2010 Altera Corporation Units = ...

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... PLL -0.795 t h -0.756 t su GCLK DIFFERENTIAL 0.872 t h 2.5-V 1.045 t GCLK SSTL CLASS II su PLL -0.795 t h © July 2010 Altera Corporation CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V -0.788 -1.107 -1.206 -1.320 -1.268 -1.539 -1.213 -1.324 -1.275 -1.576 ...

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... I/O Timing C4L I3 I4 I4L CCL CCL CCL CCL CCL CCL 1.1 V 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation Units = ...

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... GCLK 3.025 t co PLL GCLK 3.029 DIFFERENTIAL t co 1.8-V HSTL 16mA GCLK 3.025 t CLASS II co PLL © July 2010 Altera Corporation Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.286 4.658 5.066 5.583 5.443 5.661 5.193 5.710 5.572 5.729 3 ...

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... I/O Timing C4L I3 I4 I4L CCL CCL CCL CCL CCL CCL 1.1 V 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation Units = ...

Page 99

... GCLK 3.052 t co PLL GCLK 3.042 DIFFERENTIAL t co 2.5-V SSTL 16mA GCLK 3.035 t CLASS II co PLL © July 2010 Altera Corporation Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.258 4.627 5.034 5.551 5.411 5.629 5.162 5.680 5.542 5.699 3 ...

Page 100

... I/O Timing C4L I3 I4 I4L CCL CCL CCL CCL CCL CCL 1.1 V 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation Units = ...

Page 101

... GCLK 3.093 t SSTL CLASS I co PLL GCLK 3.083 t DIFFERENTIAL co 6mA 1.8-V GCLK 3.069 t SSTL CLASS I co PLL © July 2010 Altera Corporation Fast Model CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.326 4.733 5.149 5.676 5.532 5.731 5.284 5.815 5.671 5.800 3.306 4 ...

Page 102

... C4L I3 I4 I4L CCL CCL CCL CCL 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V 0.313 0.244 0.258 0.252 0.315 0.191 -0.003 -0.003 -0.004 0.191 -0.215 -0.132 -0.133 -0.136 -0.215 3.22 2.931 3.238 3.083 3.338 © July 2010 Altera Corporation Units = CCL Units = CCL ...

Page 103

... GCLK t 1.064 3.0-V h LVCMOS t -1.245 GCLK su PLL t 1.523 h t -0.923 su GCLK t 1.059 h 2 -1.240 GCLK su PLL t 1.518 h © July 2010 Altera Corporation CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V 0.123 0.177 0.192 0.207 0.198 0.105 0.156 0.175 0.195 0.185 -0.127 -0 ...

Page 104

... July 2010 Altera Corporation Units = CCL ...

Page 105

... GCLK su PLL t 1.422 h t -0.928 su GCLK t 1.064 3.0-V h PCI-X t -1.245 GCLK su PLL t 1.523 h © July 2010 Altera Corporation CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V -0.846 -1.241 -1.350 -1.474 -1.417 -1.773 -1.350 -1.474 -1.417 -1.773 0.984 1.431 1.562 1.707 1 ...

Page 106

... July 2010 Altera Corporation Units V = CCL 0 2.104 ns 1.856 2.104 ns 1.856 2.109 ns 1.851 2.109 ns 1 ...

Page 107

... GCLK su PLL t -0.826 h t -0.763 su GCLK t 0.880 1.5-V HSTL h CLASS II t 1.078 GCLK su PLL t -0.826 h © July 2010 Altera Corporation Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V -0.828 -1.172 -1.346 -1.357 -1.402 -1.641 -1.361 -1.349 -1.403 -1.679 0.961 1.360 1.553 1 ...

Page 108

... C4L I3 I4 I4L CCL CCL CCL CCL CCL 1.1 V 0.9 V 1.1 V 1.1 V 1.1 V © July 2010 Altera Corporation Units V = CCL 0 1.858 ns 2.100 1.858 ns 2.100 2.109 ns 1.851 2.109 ns 1.851 ns ns Units V = CCL ...

Page 109

... GCLK 3.233 t co 12mA GCLK 3.623 t co PLL GCLK 3.224 t co 16mA GCLK 3.614 t co PLL © July 2010 Altera Corporation Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.445 4.773 5.150 5.645 5.514 5.808 5.150 5.645 5.514 5.808 3.835 5 ...

Page 110

... I/O Timing C4L I3 I4 I4L CCL CCL CCL CCL CCL 1.1 V 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation Units = CCL ...

Page 111

... SSTL-2 10mA GCLK CLASS I 3.671 t co PLL GCLK 3.279 t co 12mA GCLK 3.669 t co PLL © July 2010 Altera Corporation Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.576 5.096 5.533 6.092 5.961 6.255 5.533 6.092 5.961 6.255 3.966 5 ...

Page 112

... I/O Timing C4L I3 I4 I4L CCL CCL CCL CCL CCL 1.1 V 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation Units = CCL ...

Page 113

... GCLK 3.268 t co 10mA GCLK 3.658 t co PLL GCLK 3.269 t co 12mA GCLK 3.659 t co PLL © July 2010 Altera Corporation Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.268 4.617 5.001 5.499 5.368 5.662 5.001 5.499 5.368 5.662 3.658 5 ...

Page 114

... I/O Timing C4L I3 I4 I4L CCL CCL CCL CCL CCL 1.1 V 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation Units = CCL ...

Page 115

... GCLK t co 2.5 V 8mA GCLK 1.327 t co PLL 3.027 GCLK t co 12mA GCLK 1.281 t co PLL © July 2010 Altera Corporation Fast Model CCL CCL CCL Commercial 1.1 V 1.1 V 1.1 V 3.481 4.833 5.216 5.678 5.579 5.814 5.256 5.802 5.703 5.896 1.650 2 ...

Page 116

... I/O Timing C4L I3 I4 I4L CCL CCL CCL CCL CCL 1.1 V 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation Units = CCL ...

Page 117

... SSTL-15 6mA GCLK CLASS I 1.254 t co PLL 3.005 GCLK t co 8mA GCLK 1.237 t co PLL © July 2010 Altera Corporation Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.284 4.636 5.022 5.516 5.390 5.652 5.141 5.635 5.508 5.728 1.457 1 ...

Page 118

... I/O Timing C4L I3 I4 I4L CCL CCL CCL CCL CCL 1.1 V 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation Units = CCL ...

Page 119

... PLL -0.890 t h -0.814 t su GCLK DIFFERENTIAL 0.933 t h 1.8-V HSTL 1.131 t GCLK CLASS I su PLL -0.878 t h © July 2010 Altera Corporation Table 1–70 list the maximum I/O timing parameters for EP3SL110 CCL CCL CCL CCL 1.1 V 1.1 V 1 ...

Page 120

... C4L I3 I4 I4L = CCL CCL CCL CCL 0.9 V 1.1 V 1.1 V 1.1 V -1.066 -1.023 -1.442 1.672 1.207 1.358 1.303 1.711 2.334 2.384 2.597 2.470 2.387 -2.032 -1.933 -1.853 © July 2010 Altera Corporation Units = CCL Units V = CCL 0 ...

Page 121

... GCLK su PLL -0.877 t h -0.733 t su GCLK DIFFERENTIAL 0.850 t h 1.5-V 1.145 t SSTL CLASS I GCLK su PLL -0.891 t h © July 2010 Altera Corporation CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V -0.950 -1.021 -0.981 -1.115 -1.070 -1.404 -0.940 1.092 1.245 1.237 1 ...

Page 122

... C4L I3 I4 I4L CCL CCL CCL CCL CCL 1.1 V 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation Units = Units = CCL ...

Page 123

... GCLK 1.315 t co PLL 3.106 GCLK t DIFFERENTIAL co 1.5-V HSTL 16mA GCLK 1.314 t CLASS II co PLL © July 2010 Altera Corporation Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V 3.330 4.687 5.079 5.586 5.447 5.731 5.200 5.706 5.570 5.803 1 ...

Page 124

... I/O Timing C4L I3 I4 I4L = CCL CCL CCL CCL CCL CCL 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation Units ...

Page 125

... GCLK 1.321 t co PLL GCLK 3.106 DIFFERENTIAL t co 2.5-V SSTL 16mA GCLK 1.314 t CLASS II co PLL © July 2010 Altera Corporation Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V 3.373 4.769 5.167 5.680 5.541 5.825 5.291 5.802 5.666 5.899 1 ...

Page 126

... I/O Timing C4L I3 I4 I4L CCL CCL CCL CCL CCL CCL 1.1 V 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation Units = ...

Page 127

... GCLK 1.371 t SSTL CLASS I co PLL GCLK 3.136 t DIFFERENTIAL co 1.8-V 6mA GCLK 1.356 t SSTL CLASS I co PLL © July 2010 Altera Corporation Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.362 4.765 5.167 5.677 5.541 5.796 5.293 5.805 5.668 5.871 1 ...

Page 128

... CCL CCL CCL CCL CCL 1.1 V 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V C4L I3 I4 I4L = CCL CCL CCL CCL 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V 0.393 0.248 0.277 0.267 0.364 4.574 4.044 4.442 4.246 4.635 © July 2010 Altera Corporation Units = Units = CCL ...

Page 129

... LVCMOS t -1.289 GCLK su PLL t 1.567 h t -0.992 su GCLK t 1.125 h 2 -1.284 GCLK su PLL t 1.562 h © July 2010 Altera Corporation CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V 0.109 0.158 0.16 0.161 0.159 0.075 0.117 0.123 0.129 0.125 -0.097 -0.137 -0.135 -0.116 -0.134 -0 ...

Page 130

... July 2010 Altera Corporation Units V = CCL 0 2.343 ns ns 3.050 ns ns 2.273 ns ns 2.980 ns ns 2.117 ns ns 2.824 ...

Page 131

... GCLK su PLL t 1.466 h t -0.997 su GCLK t 1.130 3.0-V h PCI-X t -1.289 GCLK su PLL t 1.567 h © July 2010 Altera Corporation Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V -0.895 -1.309 -1.453 -1.586 -1.565 -1.896 -1.453 -1.586 -1.565 -1.896 1.026 1.491 1.659 1.813 1.782 -1 ...

Page 132

... July 2010 Altera Corporation Units V = CCL 0 2.212 ns 1.848 2.212 ns 1.848 2.217 ns 1.843 2.217 ns 1 ...

Page 133

... GCLK su PLL t -0.822 h t -0.839 su GCLK t 0.955 1.5-V HSTL h CLASS II t 1.074 GCLK su PLL t -0.822 h © July 2010 Altera Corporation Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V -0.910 -1.280 -1.375 -1.480 -1.431 -1.752 -1.376 -1.477 -1.432 -1.791 1.041 1.464 1.582 1 ...

Page 134

... July 2010 Altera Corporation Units V = CCL 0 ...

Page 135

... PLL 3.0-V LVCMOS GCLK 3.216 t co 12mA GCLK 3.639 t co PLL GCLK 3.207 t co 16mA GCLK 3.630 t co PLL © July 2010 Altera Corporation Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.445 4.772 5.132 5.632 5.480 3.847 5.359 5.892 6 ...

Page 136

... July 2010 Altera Corporation Units = CCL ...

Page 137

... PLL GCLK 3.264 t co SSTL-2 10mA GCLK CLASS I 3.687 t co PLL GCLK 3.262 t co 12mA GCLK 3.685 t co PLL © July 2010 Altera Corporation Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.576 5.096 5.515 6.079 5.927 3.978 5.683 6.384 6 ...

Page 138

... July 2010 Altera Corporation Units = CCL ...

Page 139

... CLASS I co PLL GCLK 3.251 t co 10mA GCLK 3.674 t co PLL GCLK 3.252 t co 12mA GCLK 3.675 t co PLL © July 2010 Altera Corporation Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.268 4.617 4.983 5.486 5.334 3.670 5.204 5.648 6 ...

Page 140

... July 2010 Altera Corporation Units = CCL ...

Page 141

... GCLK t 2 8mA GCLK 1.322 t co PLL 3.038 GCLK t co 12mA GCLK 1.265 t co PLL © July 2010 Altera Corporation Fast Model CCL CCL CCL Commercial 1.1 V 1.1 V 1.1 V 3.466 4.819 5.204 5.693 5.566 5.831 5.325 5.817 5.689 5.913 1.606 1 ...

Page 142

... I/O Timing C4L I3 I4 I4L CCL CCL CCL CCL CCL 1.1 V 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation Units = CCL ...

Page 143

... GCLK t co CLASS I 6mA GCLK 1.265 t co PLL 2.998 GCLK t co 8mA GCLK 1.254 t co PLL © July 2010 Altera Corporation Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.277 4.629 5.031 5.512 5.397 5.647 5.135 5.631 5.516 5.724 1.452 1 ...

Page 144

... I/O Timing C4L I3 I4 I4L CCL CCL CCL CCL CCL 1.1 V 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation Units = CCL ...

Page 145

... GCLK DIFFERENTIAL 0.933 t h 1.8-V HSTL 1.131 t GCLK CLASS I su PLL -0.878 t h © July 2010 Altera Corporation Table 1–75 list the maximum I/O timing parameters for EP3SL150 CCL CCL CCL Commercial 1.1 V 1.1 V 1.1 V 1.1 V -1.006 -1 ...

Page 146

... July 2010 Altera Corporation Units V = CCL 0 2.040 ns 2.062 2.022 ns 2.080 2.022 ns 2.080 2.040 ns 2 ...

Page 147

... GCLK DIFFERENTIAL 0.864 t h 1.8-V 1.131 t GCLK HSTL CLASS I su PLL -0.877 t h © July 2010 Altera Corporation CCL CCL CCL Commercial 1.1 V 1.1 V 1.1 V 1.1 V -0.950 -1.021 -0.981 -1.115 -1.070 -1.404 -0.940 -1.066 -1.023 -1.442 1.092 1 ...

Page 148

... July 2010 Altera Corporation Units V = CCL 0 1.879 ns 2.170 1.862 ns 2.187 1.862 ns 2.187 1.879 ns 2 ...

Page 149

... PLL GCLK t co 12mA GCLK t co PLL GCLK t DIFFERENTIAL co 1.2-V HSTL 16mA GCLK t CLASS II co PLL © July 2010 Altera Corporation Fast Model CCL CCL CCL Commercial 1.1 V 1.1 V 1.1 V 3.100 3.330 4.687 5.079 5.586 5.447 5.731 5.200 5.706 5.570 5.803 1 ...

Page 150

... I/O Timing C4L I3 I4 I4L = CCL CCL CCL CCL CCL 1.1 V 0.9 V 1.1 V 1.1 V 1.1 V © July 2010 Altera Corporation Units V = CCL 0 ...

Page 151

... PLL GCLK t co DIFFERENTIAL 8mA GCLK t 1.8-V SSTL co PLL CLASS II GCLK t co 16mA GCLK t co PLL © July 2010 Altera Corporation Fast Model CCL CCL CCL Commercial 1.1 V 1.1 V 1.1 V 3.132 3.370 4.770 5.169 5.682 5.543 5.827 5.292 5.804 5.668 5.901 1 ...

Page 152

... I/O Timing C4L I3 I4 I4L = CCL CCL CCL CCL CCL 1.1 V 0.9 V 1.1 V 1.1 V 1.1 V © July 2010 Altera Corporation Units V = CCL 0 ...

Page 153

... DIFFERENTIAL co 6mA 1.2-V GCLK 1.338 t HSTL CLASS I co PLL GCLK 3.114 t co 8mA GCLK 1.334 t co PLL © July 2010 Altera Corporation Fast Model CCL CCL CCL Commercial 1.1 V 1.1 V 1.1 V 2.894 4.033 4.387 4.843 4.717 4.978 4.486 4.943 4.816 5.035 1 ...

Page 154

... I/O Timing C4L I3 I4 I4L CCL CCL CCL CCL CCL CCL 1.1 V 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation Units = ...

Page 155

... DIFFERENTIAL co 12mA 2.5-V GCLK 1.340 t SSTL CLASS I co PLL GCLK 3.106 t co 16mA GCLK 1.326 t co PLL © July 2010 Altera Corporation Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.396 4.805 5.209 5.720 5.584 5.839 5.335 5.849 5.712 5.915 1 ...

Page 156

... CCL 0.9 V 1.1 V 1.1 V 1.1 V -1.934 2.724 2.008 2.259 2.177 -2.477 3.543 2.776 3.113 3.000 -1.934 2.724 2.008 2.259 2.177 -2.477 3.543 2.776 3.113 3.000 © July 2010 Altera Corporation Units V = CCL 0.9 V 0.495 ns 4.707 Units V = CCL 0 Units V = CCL ...

Page 157

... GCLK su PLL t 1.717 h t -1.066 su GCLK t 1.216 SSTL-18 h CLASS I t -1.396 GCLK su PLL t 1.711 h © July 2010 Altera Corporation CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V -1.184 -1.809 -1.777 -2.001 -1.933 -2.481 -1.777 -2.001 1.330 2.031 2.010 2.258 2.176 -1 ...

Page 158

... July 2010 Altera Corporation Units V = CCL 0 2.509 ns ns 3.328 ns ns 2.490 ns ns 3.309 ns ns 2.490 ns ns 3.309 ...

Page 159

... V t 0.921 GCLK su PLL t -0.644 h t -1.322 su GCLK t 0.891 h 1 1.457 GCLK su PLL t -1.312 h © July 2010 Altera Corporation CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V -1.184 -1.809 -1.777 -2.001 -1.933 -2.481 -1.777 -2.001 1.330 2.031 2.010 2.258 2.176 -1.476 -2 ...

Page 160

... July 2010 Altera Corporation Units V = CCL 0.9 V 2.755 ns ns 1.977 ns 2.764 2.747 ns 1.973 ns 1.973 2.747 ns 1 ...

Page 161

... GCLK su PLL t 1.438 h t 0.909 su GCLK t -0.632 3.0-V h PCI-X t -1.304 GCLK su PLL t 1.438 h © July 2010 Altera Corporation Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V 1.025 -1.969 -1.407 -1.654 -1.576 -1.475 -1.381 -1.551 -1.576 -1.475 1.384 1.674 -1.873 -2.118 -2.040 -2.463 -1.994 -2.144 -2.040 -2.463 -1 ...

Page 162

... I/O Timing C4L I3 I4 I4L CCL CCL CCL CCL CCL 1.1 V 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation Units = CCL ...

Page 163

... GCLK 3.533 t co 12mA GCLK 3.932 t co PLL GCLK 3.495 t co 16mA GCLK 3.894 t co PLL © July 2010 Altera Corporation Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.555 5.173 5.360 5.861 5.719 6.123 5.360 5.861 5.719 6.123 3.954 5 ...

Page 164

... I/O Timing C4L I3 I4 I4L CCL CCL CCL CCL CCL 1.1 V 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation Units = CCL ...

Page 165

... GCLK 3.503 t co 10mA GCLK 3.902 t co PLL GCLK 3.503 t co 12mA GCLK 3.902 t co PLL © July 2010 Altera Corporation Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.730 5.556 5.815 6.395 6.252 6.657 5.815 6.395 6.252 6.657 4.129 6 ...

Page 166

... I/O Timing C4L I3 I4 I4L CCL CCL CCL CCL CCL 1.1 V 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation Units = CCL ...

Page 167

... GCLK 3.906 t co PLL GCLK 3.505 t 1.5-V co 16mA HSTL GCLK 3.904 t CLASS II co PLL © July 2010 Altera Corporation Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.516 5.153 5.348 5.856 5.713 6.118 5.348 5.856 5.713 6.118 3.915 5 ...

Page 168

... I/O Timing C4L I3 I4 I4L CCL CCL CCL CCL CCL 1.1 V 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation Units = CCL ...

Page 169

... GCLK 3.516 t 2 8mA GCLK 1.436 t co PLL 3.463 GCLK t co 12mA GCLK 1.379 t co PLL © July 2010 Altera Corporation Fast Model CCL CCL CCL Commercial 1.1 V 1.1 V 1.1 V 3.902 5.663 5.916 6.397 6.238 6.709 6.053 6.634 6.238 6.709 1.768 2 ...

Page 170

... I/O Timing C4L I3 I4 I4L CCL CCL CCL CCL CCL CCL 1.1 V 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation Units = ...

Page 171

... CLASS I 6mA GCLK 1.379 t co PLL 3.448 GCLK t co 8mA GCLK 1.368 t co PLL © July 2010 Altera Corporation Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.748 5.512 5.727 6.306 6.146 6.491 5.870 6.440 6.146 6.491 1.596 2 ...

Page 172

... I/O Timing C4L I3 I4 I4L CCL CCL CCL CCL CCL CCL 1.1 V 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation Units = ...

Page 173

... GCLK DIFFERENTIAL 1.297 t h 1.8-V HSTL 1.095 t GCLK CLASS I su PLL -0.816 t h © July 2010 Altera Corporation Table 1–88 list the maximum I/O timing parameters for EP3SL200 CCL CCL CCL CCL Commercial 1.1 V 1.1 V 1 ...

Page 174

... July 2010 Altera Corporation Units = ...

Page 175

... DIFFERENTIAL PLL -0.774 t h 1.5-V -1.146 t HSTL CLASS I su GCLK 1.283 t h 1.055 t GCLK su PLL -0.774 t h © July 2010 Altera Corporation CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V -1.401 -1.719 -1.648 -1.841 -1.769 -2.221 -1.630 -1.815 -1.769 -2.221 1.563 1 ...

Page 176

... July 2010 Altera Corporation Units = CCL ...

Page 177

... PLL GCLK t co 12mA GCLK t co PLL DIFFERENTIAL GCLK t co 1.2-V HSTL 16mA GCLK t CLASS II co PLL © July 2010 Altera Corporation Fast Model CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.479 3.750 5.506 5.712 6.270 6.106 6.513 5.854 6.411 6.106 6.513 3 ...

Page 178

... I/O Timing C4L I3 I4 I4L CCL CCL CCL CCL CCL CCL 1.1 V 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation Units = ...

Page 179

... PLL GCLK t co DIFFERENTIAL 8mA GCLK t 1.8-V SSTL co PLL CLASS II GCLK t co 16mA GCLK t co PLL © July 2010 Altera Corporation Fast Model CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.506 3.783 5.577 5.790 6.354 6.190 6.597 5.934 6.497 6.190 6.597 3.496 3 ...

Page 180

... I/O Timing C4L I3 I4 I4L CCL CCL CCL CCL CCL CCL 1.1 V 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation Units = ...

Page 181

... DIFFERENTIAL co 1.2-V 6mA GCLK 3.577 t HSTL CLASS I co PLL GCLK 3.553 t co 8mA GCLK 3.535 t co PLL © July 2010 Altera Corporation Fast Model CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.376 4.936 5.115 5.637 5.478 5.865 5.239 5.762 5.478 5.865 3.812 5 ...

Page 182

... I/O Timing C4L I3 I4 I4L CCL CCL CCL CCL CCL CCL 1.1 V 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation Units = ...

Page 183

... GCLK 3.568 t co PLL GCLK 3.550 t DIFFERENTIAL co 2.5-V 16mA GCLK 3.536 t SSTL CLASS II co PLL © July 2010 Altera Corporation Fast Model CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.829 5.658 5.872 6.445 6.278 6.657 6.024 6.599 6.278 6.657 3.839 5.659 5.873 6.444 6.277 6.656 6.023 6.597 6.277 6.656 3 ...

Page 184

... CCL CCL CCL 0.9 V 1.1 V 1.1 V 1.1 V 2.783 2.284 2.574 2.476 2.783 3.912 3.081 3.434 3.313 3.912 2.783 2.284 2.574 2.476 2.783 3.912 3.081 3.434 3.313 3.912 © July 2010 Altera Corporation Units = CCL Units V = CCL 0.9 V 0.547 ns 0.306 Units V = CCL 0 ...

Page 185

... GCLK su PLL t 1.935 h t -1.276 su GCLK t 1.419 SSTL-18 h CLASS I t -1.622 GCLK su PLL t 1.929 h © July 2010 Altera Corporation Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V -1.346 -2.016 -2.063 -2.329 -2.244 -2.541 -2.063 -2.329 -2.244 -2.541 1.487 2.231 2.286 2 ...

Page 186

... July 2010 Altera Corporation Units V = CCL 0 3.023 ns 1.679 3.023 ns 1.679 3.023 ns 1.679 3.023 ns 1 ...

Page 187

... V t 0.885 GCLK su PLL t -0.621 h t -1.251 su GCLK t 1.377 h 1 0.827 GCLK su PLL t -0.562 h © July 2010 Altera Corporation Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V -1.346 -2.016 -2.063 -2.329 -2.244 -2.541 -2.063 -2.329 -2.244 -2.541 1.487 2.231 2.286 2.573 2.475 -1 ...

Page 188

... July 2010 Altera Corporation Units V = CCL 0 2.794 ns 1.684 2.639 ns 1.839 2.561 ns 1.948 2.561 ns 1 ...

Page 189

... GCLK su PLL t -0.609 h t -1.245 su GCLK t 1.368 3.0-V h PCI-X t 0.873 GCLK su PLL t -0.609 h © July 2010 Altera Corporation Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V -1.232 -1.824 -1.825 -1.954 -1.887 -2.333 -1.833 -1.964 -1.908 -2.377 1.371 2.038 2.044 2.195 2 ...

Page 190

... July 2010 Altera Corporation ...

Page 191

... PLL 2.5 V GCLK 3.561 t co 12mA GCLK 4.127 t co PLL GCLK 3.523 t co 16mA GCLK 4.088 t co PLL © July 2010 Altera Corporation C4L CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V 3.583 5.243 5.427 5.947 5.800 4.149 6.087 6.279 6 ...

Page 192

... July 2010 Altera Corporation ...

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... CLASS I 4.107 t co PLL GCLK 3.531 t co 10mA GCLK 4.095 t co PLL GCLK 3.531 t co 12mA GCLK 4.095 t co PLL © July 2010 Altera Corporation C4L CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V 3.758 5.626 5.882 6.481 6.333 4.322 6.468 6.731 7 ...

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... July 2010 Altera Corporation ...

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... PLL GCLK 3.535 t co 12mA GCLK 4.098 t co PLL GCLK 3.533 t 1.5-V co HSTL 16mA GCLK 4.096 t CLASS II co PLL © July 2010 Altera Corporation C4L CCL CCL CCL CCL 1.1 V 1.1 V 1.1 V 1.1 V 3.544 5.223 5.415 5.942 5.794 4.108 6.064 6.263 6 ...

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... July 2010 Altera Corporation ...

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... GCLK 3.381 t 2 8mA GCLK 1.464 t co PLL 3.324 GCLK t co 12mA GCLK 1.407 t co PLL © July 2010 Altera Corporation Fast Model CCL CCL CCL Commercial 1.1 V 1.1 V 1.1 V 3.781 5.469 5.657 6.238 6.095 6.481 5.741 6.370 6.120 6.565 1.782 2 ...

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... I/O Timing C4L I3 I4 I4L CCL CCL CCL CCL CCL CCL 1.1 V 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation Units = ...

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... GCLK 3.364 t co CLASS I 6mA GCLK 1.407 t co PLL 3.353 GCLK t co 8mA GCLK 1.396 t co PLL © July 2010 Altera Corporation Fast Model Commercial CCL CCL CCL 1.1 V 1.1 V 1.1 V 3.598 5.289 5.499 6.054 5.911 6.297 5.651 6.181 6.034 6.376 1 ...

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... I/O Timing C4L I3 I4 I4L CCL CCL CCL CCL CCL CCL 1.1 V 0.9 V 1.1 V 1.1 V 1.1 V 0.9 V © July 2010 Altera Corporation Units = ...