EP3SL150F780C4N Altera, EP3SL150F780C4N Datasheet - Page 16
EP3SL150F780C4N
Manufacturer Part Number
EP3SL150F780C4N
Description
IC STRATIX III FPGA 150K 780FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
4.EP3SL150F780C4N.pdf
(341 pages)
Specifications of EP3SL150F780C4N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
488
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Stratix III
Number Of Logic Blocks/elements
142500
# I/os (max)
488
Frequency (max)
450MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.1V
Logic Cells
142500
Ram Bits
6543360
Operating Supply Voltage (min)
1.05V
Operating Supply Voltage (max)
1.15V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2403
EP3SL150F780C4NES
EP3SL150F780C4NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F780C4N
Manufacturer:
ALTERA
Quantity:
3 000
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1–6
Table 1–6. Bus Hold Parameters for Stratix III Devices (Part 2 of 2)
Table 1–7. On-Chip Termination Calibration Accuracy Specifications for Stratix III Devices
Stratix III Device Handbook, Volume 2
High overdrive
current
Bus-hold trip
point
25- R
3.3, 3.0, 2.5, 1.8, 1.5, 1.2
50- R
3.3, 3.0, 2.5, 1.8, 1.5, 1.2
50- R
20-R
3.3, 3.0, 2.5, 1.8, 1.5, 1.2
25- R
R
Notes to
(1) OCT calibration accuracy is valid at the time of calibration only.
(2) 25-
(3) 1.5 V and 1.2 V only supports 40-
(4) For resistance tolerance after power-up calibration, refer to
OCT_CAL
Parameter
S
S
T
S
S _left_shift
Table
(2)
2.5, 1.8, 1.5, 1.2
to 60-R
R
S
Symbol
not supported for 1.5 V and 1.2 V in Row I/O.
1–7:
Symbol
S
V
I
ODH
TRIP
On-Chip Termination (OCT) Specifications
If you enable OCT calibration, calibration is automatically performed at power-up for
the I/Os connected to the calibration block.
calibration block accuracy specifications.
0V <V
Conditions
Internal series termination with
calibration (25- setting)
Internal series termination with
calibration (50- setting)
Internal parallel termination with
calibration (50- setting)
Expanded range for internal
series termination with
calibration
(Between 20- to 60-setting)
Internal left shift series
termination with calibration
(25- R
Internal series termination with
calibration
—
IN
to 60-
<V
CCIO
S _left_shift
Description
expanded range.
Min
0.45
—
setting)
1.2 V
Max
-120
0.95
Equation 1–1
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
Min
0.50
—
1.5 V
and
V
3.3, 3.0, 2.5, 1.8, 1.5, 1.2 V
V
3.3, 3.0, 2.5, 1.8, 1.5, 1.2 V
V
V
3.3, 3.0, 2.5, 1.8, 1.5, 1.2 V
(3)
V
3.3, 3.0, 2.5, 1.8, 1.5, 1.2 V
Max
-160
1.00
CCIO
CCIO
CCIO
CCIO
CCIO
Table 1–9 on page
=
=
= 2.5, 1.8, 1.5, 1.2 V
=
=
Table 1–7
Min
0.68
Conditions
—
1.8 V
V
CCIO
Max
-200
1.07
1–8.
lists the Stratix III OCT
Min
0.70
(Note 1)
—
2.5 V
(4)
© July 2010 Altera Corporation
Max
-300
1.70
±10
±10
±10
C2
±8
±8
Calibration
Accuracy
Electrical Characteristics
3.0 V/3.3 V
Min
0.80
±10
±10
±10
—
C3,
±8
±8
I3
Max
-500
2.00
±10
±10
±10
C4,
±8
±8
I4
Unit
Unit
µA
%
%
%
%
%
V
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