EP3SL150F780C4N Altera, EP3SL150F780C4N Datasheet - Page 321

• Manufacturer Part Number: EP3SL150F780C4N
• Description: IC STRATIX III FPGA 150K 780FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F780C4N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 488
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Stratix III
• Number Of Logic Blocks/elements: 142500
• # I/os (max): 488
• Frequency (max): 450MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.1V
• Logic Cells: 142500
• Ram Bits: 6543360
• Operating Supply Voltage (min): 1.05V
• Operating Supply Voltage (max): 1.15V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2403; EP3SL150F780C4NES

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–144. EP3SL50 Column Pin Regional Clock Timing Specifications (Part 2 of 2)
Table 1–145. EP3SL50 Row Pin Regional Clock Timing Specifications
Table 1–146. EP3SL50 Column Pin Periphery Clock Timing Specifications
Table 1–147. EP3SL50 Row Pin Periphery Clock Timing Specifications
© July 2010 Altera Corporation
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Parameter
Parameter
Parameter
Parameter
PLLCIN
PLLCOUT
CIN
COUT
PLLCIN
PLLCOUT
CIN
COUT
PLLCIN
PLLCOUT
CIN
COUT
PLLCIN
PLLCOUT
Industrial
Industrial
Industrial
Industrial
-0.019
-0.019
-0.064
-0.081
-0.081
-0.014
-0.096
1.636
1.554
0.018
1.468
1.468
1.482
1.400
Fast Model
Fast Model
Fast Model
Fast Model
Table 1–146
devices.
Commercial
Commercial
Commercial
Commercial
-0.025
-0.025
-0.007
-0.081
-0.081
-0.049
1.729
1.638
0.084
1.469
1.469
1.556
1.465
0.042
and
Table 1–147
-0.264 -0.315 -0.256
-0.264 -0.315 -0.256
-0.178 -0.255 -0.222
-0.320 -0.418 -0.403
-0.327 -0.383 -0.334
-0.327 -0.383 -0.334
-0.222 -0.299 -0.278
-0.364 -0.462 -0.459
2.356
2.214
2.143
2.143
2.223
2.078
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
C2
C2
C2
C2
CCL
CCL
CCL
CCL
=
=
=
=
2.567
2.404
2.418
2.418
2.488
2.325
1.1 V
1.1 V
1.1 V
V
V
V
V
1.1V
C3
C3
C3
C3
CCL
CCL
CCL
CCL
list the periphery clock timing parameters for EP3SL50
=
=
=
=
2.894
2.713
2.797
2.797
2.859
2.678
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
C4
C4
C4
C4
CCL
CCL
CCL
CCL
=
=
=
=
-0.236
-0.236
-0.169
-0.340
-0.310
-0.310
-0.224
-0.395
2.800
2.629
2.668
2.668
2.740
2.569
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
CCL
CCL
CCL
CCL
=
=
=
=
C4L
C4L
C4L
C4L
-0.017
-0.017
-0.226
-0.385
-0.105
-0.105
-0.295
-0.454
2.964
2.805
3.219
3.219
3.034
2.875
0.9 V
0.9 V
0.9 V
0.9 V
V
V
V
V
CCL
CCL
CCL
CCL
=
=
=
=
-0.315
-0.315
-0.203
-0.373
-0.383
-0.383
-0.256
-0.426
2.622
2.452
2.418
2.418
2.539
2.369
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
I3
CCL
I3
CCL
I3
CCL
I3
CCL
Stratix III Device Handbook, Volume 2
=
=
=
=
0.224
0.224
2.941
2.752
0.298
0.109
2.801
2.801
0.273
0.273
2.897
2.708
0.368
0.179
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
I4
CCL
I4
CCL
I4
CCL
I4
CCL
=
=
=
=
-0.236 -0.017
-0.236 -0.017
-0.123 -0.272
-0.302 -0.431
-0.310 -0.105
-0.310 -0.105
-0.177 -0.257
-0.356 -0.416
2.853
2.674
2.668
2.668
2.785
2.606
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
CCL
CCL
CCL
CCL
=
=
=
=
I4L
I4L
I4L
I4L
2.997
2.838
3.219
3.219
3.056
2.897
0.9 V
0.9 V
0.9 V
0.9 V
V
V
V
V
1–311
CCL
CCL
CCL
CCL
=
=
=
=
Units
Units
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns