EP3SL150F780C4N Altera, EP3SL150F780C4N Datasheet - Page 154

• Manufacturer Part Number: EP3SL150F780C4N
• Description: IC STRATIX III FPGA 150K 780FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F780C4N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 488
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Stratix III
• Number Of Logic Blocks/elements: 142500
• # I/os (max): 488
• Frequency (max): 450MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.1V
• Logic Cells: 142500
• Ram Bits: 6543360
• Operating Supply Voltage (min): 1.05V
• Operating Supply Voltage (max): 1.15V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2403; EP3SL150F780C4NES

6–6
Figure 6–8. Periphery Clock Networks (EP3SE260 Devices)
Figure 6–9. Periphery Clock Networks (EP3SL340 Devices)
Stratix III Device Handbook, Volume 1
Clocking Regions
Stratix III devices provide up to 104 distinct clock domains (16 GCLKs + 88 RCLKs) in
the entire device. You can utilize these clock resources to form the following three
different types of clock regions:
■
■
■
Entire device clock region
Regional clock region
Dual-regional clock region
CLK[0..3]
CLK[0..3]
L1
L2
L3
L4
L1
L2
L3
L4
PCLK[28..41]
PCLK[14..27]
PCLK[42..55]
PCLK[0..15]
PCLK[33..49]
PCLK[50..65]
PCLK[0..13]
PCLK[16..32]
CLK[12..15]
CLK[12..15]
Q1
Q4
Q1
Q4
CLK[4..7]
CLK[4..7]
T1
B1
T1
B1
T2
B2
T2
B2
Q2
Q3
Q2
Q3
PCLK[116..131]
PCLK[98..111]
PCLK[99..115]
PCLK[84..97]
PCLK[70..83]
PCLK[56..69]
PCLK[66..81]
PCLK[82..98]
Chapter 6: Clock Networks and PLLs in Stratix III Devices
R1
R2
R3
R4
R1
R2
R3
R4
CLK[8..11]
CLK[8..11]
Clock Networks in Stratix III Devices
© July 2010 Altera Corporation