EP3SL150F780C4N Altera, EP3SL150F780C4N Datasheet - Page 157

• Manufacturer Part Number: EP3SL150F780C4N
• Description: IC STRATIX III FPGA 150K 780FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F780C4N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 488
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Stratix III
• Number Of Logic Blocks/elements: 142500
• # I/os (max): 488
• Frequency (max): 450MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.1V
• Logic Cells: 142500
• Ram Bits: 6543360
• Operating Supply Voltage (min): 1.05V
• Operating Supply Voltage (max): 1.15V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2403; EP3SL150F780C4NES

Chapter 6: Clock Networks and PLLs in Stratix III Devices
Clock Networks in Stratix III Devices
Table 6–3. Clock Input Pin Connectivity to Regional Clock Networks (Quadrant 1)
Table 6–4. Clock Input Pin Connectivity to Regional Clock Networks (Quadrant 2) (Part 1 of 2)
© July 2010
RCLK0
RCLK1
RCLK2
RCLK3
RCLK4
RCLK5
RCLK54
RCLK55
RCLK56
RCLK57
RCLK58
RCLK59
RCLK60
RCLK61
RCLK62
RCLK63
RCLK38
RCLK39
RCLK40
RCLK41
RCLK42
RCLK43
RCLK44
RCLK45
RCLK46
RCLK47
RCLK48
RCLK49
Clock Resource
Clock Resource
Altera Corporation
Table 6–3
device Quadrant 1. A given clock input pin can drive two adjacent regional clock
networks to create a dual-regional clock network.
Table 6–4
device Quadrant 2. A given clock input pin can drive two adjacent regional clock
networks to create a dual-regional clock network.
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lists the connectivity between the dedicated clock input pins and RCLKs in
lists the connectivity between the dedicated clock input pins and RCLKs in
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CLK (p/n Pins)
CLK (p/n Pins)
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Stratix III Device Handbook, Volume 1
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