EP3SL150F780C4N Altera, EP3SL150F780C4N Datasheet - Page 278

• Manufacturer Part Number: EP3SL150F780C4N
• Description: IC STRATIX III FPGA 150K 780FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F780C4N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 488
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Stratix III
• Number Of Logic Blocks/elements: 142500
• # I/os (max): 488
• Frequency (max): 450MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.1V
• Logic Cells: 142500
• Ram Bits: 6543360
• Operating Supply Voltage (min): 1.05V
• Operating Supply Voltage (max): 1.15V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2403; EP3SL150F780C4NES

8–30
Figure 8–14. Example of a DQS Update Enable Waveform
Stratix III Device Handbook, Volume 1
(Updated every 8 cycles)
DQS Delay Settings
Update Enable
Circuitry Output
System Clock
DLL Counter Update
(Every 8 cycles)
You can also bypass the DQS delay chain to achieve 0° phase shift.
Update Enable Circuitry
Both the DQS delay settings and phase-offset settings pass through a register before
going into the DQS delay chains. The registers are controlled by the update enable
circuitry to allow enough time for any changes in the DQS delay setting bits to arrive
at all the delay elements. This allows them to be adjusted at the same time. The update
enable circuitry enables the registers to allow enough time for the DQS delay settings
to travel from the DQS phase-shift circuitry or core logic to all the DQS logic blocks
before the next change. It uses the input reference clock or a user clock from the core
to generate the update enable output. The ALTMEMPHY megafunction uses this
circuit by default. See
circuitry output.
DQS Postamble Circuitry
For external memory interfaces that use a bi-directional read strobe like DDR3, DDR2,
and DDR SDRAM, the DQS signal is low before going to or coming from a
high-impedance state. The state where DQS is low, just after a high-impedance state,
is called the preamble. The state where DQS is low, just before it returns to a
high-impedance state, is called the postamble. There are preamble and postamble
specifications for both read and write operations in DDR3, DDR2, and DDR SDRAM.
The DQS postamble circuitry ensures that the data is not lost if there is noise on the
DQS line during the end of a read operation that occurs while the DQS is in a
postamble state.
Stratix III devices have a dedicated postamble register that you can control to ground
the shifted DQS signal used to clock the DQ input registers at the end of a read
operation. This ensures that any glitches on the DQS input signals at the end of the
read postamble time do not affect the DQ IOE registers.
In addition to the dedicated postamble register, Stratix III devices also have an HDR
block inside the postamble enable circuitry. These registers are used if the controller is
running at half the frequency of the I/Os.
Figure 8–14
6 bit
for an example waveform of the update enable
Chapter 8: External Memory Interfaces in Stratix III Devices
DLL Counter Update
(Every 8 cycles)
Stratix III External Memory Interface Features
© March 2010 Altera Corporation