EP3SL150F780C4N Altera, EP3SL150F780C4N Datasheet - Page 289

• Manufacturer Part Number: EP3SL150F780C4N
• Description: IC STRATIX III FPGA 150K 780FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F780C4N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 488
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Stratix III
• Number Of Logic Blocks/elements: 142500
• # I/os (max): 488
• Frequency (max): 450MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.1V
• Logic Cells: 142500
• Ram Bits: 6543360
• Operating Supply Voltage (min): 1.05V
• Operating Supply Voltage (max): 1.15V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2403; EP3SL150F780C4NES

Chapter 8: External Memory Interfaces in Stratix III Devices
Stratix III External Memory Interface Features
I/O Configuration Block and DQS Configuration Block
Figure 8–25. I/O Configuration Block and DQS Configuration Block
Table 8–11. I/O Configuration Block Bit Sequence
© March 2010 Altera Corporation
15..17
19..22
datain
clk
7..10
0..3
4..6
Bit
11
12
13
14
18
ena
The I/O configuration block and the DQS configuration block are shift registers that
you can use to dynamically change the settings of various device configuration bits.
The shift registers power-up low. Every I/O pin contains one I/O configuration
register, while every DQS pin contains one DQS configuration block in addition to the
I/O configuration register.
DQS configuration block circuitry.
Table 8–11
lists the I/O configuration block bit sequence.
update
Figure 8–25
bit 0
padtoinputregisterdelaysetting[0..3]
padtoinputregisterfinedelaysetting
dutycyclecorrectionsetting[3..0]
outputonlydelaysetting2[2..0]
outputonlyfinedelaysetting2
outputdelaysetting1[0..3]
outputdelaysetting2[0..2]
dutycyclecorrectionmode
outputfinedelaysetting1
outputfinedelaysetting2
shows the I/O configuration block and the
Bit Name
bit 1
#
Stratix III Device Handbook, Volume 1
dataout
8–41