EP3SL150F780C4N Altera, EP3SL150F780C4N Datasheet - Page 321

• Manufacturer Part Number: EP3SL150F780C4N
• Description: IC STRATIX III FPGA 150K 780FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F780C4N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 488
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Stratix III
• Number Of Logic Blocks/elements: 142500
• # I/os (max): 488
• Frequency (max): 450MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.1V
• Logic Cells: 142500
• Ram Bits: 6543360
• Operating Supply Voltage (min): 1.05V
• Operating Supply Voltage (max): 1.15V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2403; EP3SL150F780C4NES

Chapter 9: High-Speed Differential I/O Interfaces and DPA in Stratix III Devices
Chapter Revision History
Chapter Revision History
Table 9–4. Chapter Revision History
© July 2010
July 2010
March 2010
May 2009
February 2009
October 2008
May 2008
November 2007
October 2007
May 2007
November 2006
Date
Altera Corporation
Table 9–4
Revision
lists the revision history for this chapter.
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
Updated
Updated for the Quartus II software version 9.1 SP2 release:
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Initial release.
Updated “LVDS Channels”, “Differential Transmitter”, and “Differential
Receiver” section.
Minor changes to the text.
Updated Table 9–1 and Table 9–2.
Updated Figure 9–5.
Updated “DPA-Enabled Channels and Single-Ended I/Os” section.
Updated “DPA-Enabled Channels and Single-Ended I/Os” section.
Updated Table 9–2.
Removed “Reference Documents” section.
Updated “Introduction”, “Differential Receiver”, and “Synchronizer”
sections.
Updated Figure 9–5.
Updated New Document Format.
Updated “Soft-CDR Mode”, “Dynamic Phase Aligner (DPA)”,
“Programmable Pre-Emphasis and Programmable VOD”, and
“Guidelines for DPA-Enabled Differential Channels” sections.
Updated Table 9–1 and Table 9–2.
Removed “Figure 9–19. Left/Right PLL Driving Distance for
DPA-Enabled Channels”.
Updated Table 9–1 and Table 9–2.
Added material to “DPA-Enabled Channels and Single-Ended I/Os” on
page 9–21 and removed material from “DPA-Disabled Channels and
Single-Ended I/Os” on page 9–29.
Added new sections “Programmable Pre-Emphasis and
Programmable VOD” on page 9–12, “Soft-CDR Mode”, and
“Referenced Documents”.
Added live links for references.
Added Figure 9–10.
Minor edits to “DPA-Enabled Channel Driving Distance” section.
Minor changes to second paragraph of the section “Differential I/O
Termination”.
Added Table 9–1 and Table 9–2.
“Differential Transmitter”
Changes Made
and
“Differential Receiver”
Stratix III Device Handbook, Volume 1
sections.
9–27