EP3SL150F780C4N Altera, EP3SL150F780C4N Datasheet - Page 339

• Manufacturer Part Number: EP3SL150F780C4N
• Description: IC STRATIX III FPGA 150K 780FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F780C4N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 488
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Stratix III
• Number Of Logic Blocks/elements: 142500
• # I/os (max): 488
• Frequency (max): 450MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.1V
• Logic Cells: 142500
• Ram Bits: 6543360
• Operating Supply Voltage (min): 1.05V
• Operating Supply Voltage (max): 1.15V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2403; EP3SL150F780C4NES

Chapter 11: Configuring Stratix III Devices
Configuration Features
Remote System Upgrade
Power-On Reset Circuit
V
V
© March 2011 Altera Corporation
CCPGM
CCPD
Pins
Pins
f
f
1
Stratix III devices contain the remote update feature. For more information about this
feature, refer to the
Stratix III Device Handbook.
The POR circuit keeps the entire system in reset until the power supply voltage levels
have stabilized on power-up. On power-up, the device does not release nSTATUS
until V
power down, brown-out occurs if V
and V
In Stratix III devices, a pin-selectable option (PORSEL) is provided that allows you to
select a typical POR time setting of 12 ms or 100 ms. In both cases, you can extend the
POR time by using an external component to assert the nSTATUS pin low.
Stratix III devices offer a new power supply, V
pins and dual function pins. The configuration voltages supported are 1.8 V, 2.5 V,
3.0 V, and 3.3 V. Stratix III devices do not support the 1.5 V configuration.
Use this pin to power all dedicated configuration inputs, dedicated configuration
outputs, dedicated configuration bi-directional pins, and some of the dual functional
pins that you use for configuration. With V
have to share power lines with the regular I/O buffer in Stratix III devices.
The operating voltage for the configuration input pin is independent of the I/O
bank’s power supply V
voltage constraints on V
Stratix III devices have a dedicated programming power supply, V
connected to 3.3 V/3.0 V/2.5 V to power the I/O pre-drivers, the JTAG input and
output pins (TCK, TMS, TDI, TDO, and TRST), and the design security circuitry.
V
these supplies are not ramped up within this specified time, your Stratix III device
will not configure successfully. If your system does not allow ramp-up time of 100 ms
or less, you must hold nCONFIG low until all power supplies are stable.
For more information about the configuration pins power supply, refer to
Configuration Pins” on page
CCPGM
CC
CCPT
and V
, V
, V
CCPD
CCL
CCPD
, or V
, V
must ramp up from 0 V to the desired voltage level within 100 ms. If
CC
Remote System Upgrades with Stratix III Devices
CCPGM
, V
CCPD
CCIO
CCIO
drops below the threshold voltage.
, and V
during the configuration. Therefore, no configuration
are needed in Stratix III devices.
11–43.
CCPGM
CC
or V
are above the device’s POR trip point. On
CCL
CCPGM
ramps down below the POR trip point
CCPGM
, configuration input buffers do not
, for all the dedicated configuration
Stratix III Device Handbook, Volume 1
in volume 1 of the
CCPD
, which must be
“Device
11–7