EP3SL150F780C4N Altera, EP3SL150F780C4N Datasheet - Page 344

• Manufacturer Part Number: EP3SL150F780C4N
• Description: IC STRATIX III FPGA 150K 780FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F780C4N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 488
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Stratix III
• Number Of Logic Blocks/elements: 142500
• # I/os (max): 488
• Frequency (max): 450MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.1V
• Logic Cells: 142500
• Ram Bits: 6543360
• Operating Supply Voltage (min): 1.05V
• Operating Supply Voltage (max): 1.15V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2403; EP3SL150F780C4NES

11–12
Figure 11–4. Multi-Device FPP Configuration Using an External Host
Note to
(1) Connect the resistor to a supply that provides an acceptable input signal for all Stratix III devices on the chain. V
Stratix III Device Handbook, Volume 1
meet the V
Figure
(MAX II Device or
Microprocessor)
External Host
ADDR DATA[7..0]
IH
11–4:
Memory
specification of the I/O on the external host. It is recommended to power up all configuration system’s I/O with V
Figure 11–4
circuit is similar to the FPP configuration circuit for a single device, except the
Stratix III devices are cascaded for multi-device configuration.
In a multi-device FPP configuration, the first device’s nCE pin is connected to GND
while its nCEO pin is connected to nCE of the next device in the chain. The last
device’s nCE input comes from the previous device, while its nCEO pin is left floating.
After the first device completes configuration in a multi-device configuration chain,
its nCEO pin drives low to activate the second device’s nCE pin, which prompts the
second device to begin configuration. The second device in the chain begins
configuration within one clock cycle; therefore, the transfer of data destinations is
transparent to the MAX II device. All other configuration pins (nCONFIG, nSTATUS,
DCLK, DATA[7..0], and CONF_DONE) are connected to every device in the chain. The
configuration signals may require buffering to ensure signal integrity and prevent
clock skew problems. Ensure that the DCLK and DATA lines are buffered for every
fourth device. Because all device CONF_DONE pins are tied together, all devices
initialize and enter user mode at the same time.
All nSTATUS and CONF_DONE pins are tied together. If any device detects an error,
configuration stops for the entire chain and you must reconfigure the entire chain. For
example, if the first device flags an error on nSTATUS, it resets the chain by pulling its
nSTATUS pin low. This behavior is similar to a single device detecting an error.
If the Auto-restart configuration after error option is turned on, the devices release
their nSTATUS pins after a reset time-out period (maximum of 100 μs). After all
nSTATUS pins are released and pulled high, the MAX II device tries to reconfigure the
chain without pulsing nCONFIG low. If this option is turned off, the MAX II device
must generate a low-to-high transition (with a low pulse of at least 2 μs) on nCONFIG
to restart the configuration process.
V
10 kΩ
CCPGM
(1)
shows how to configure multiple devices using a MAX II device. This
V
CCPGM
10 kΩ
GND
(1)
CONF_DONE
nSTATUS
nCE
DATA[7..0]
nCONFIG
DCLK
Stratix III Device 1
MSEL[2..0]
nCEO
GND
Chapter 11: Configuring Stratix III Devices
© March 2011 Altera Corporation
CONF_DONE
nSTATUS
nCE
nCONFIG
DCLK
DATA[7..0]
Fast Passive Parallel Configuration
Stratix III Device 2
CCPGM
should be high enough to
MSEL[2..0]
nCEO
CCPGM
.
GND
N.C.