EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 15

IC STRATX III FPGA 150K 1152FBGA

EP3SL150F1152C3N

Manufacturer Part Number

EP3SL150F1152C3N

Description

IC STRATX III FPGA 150K 1152FBGA

Manufacturer

Altera

Series

Stratix® IIIr

Datasheets

1.EP3SL150F780C4N.pdf (16 pages)

2.EP3SL150F780C4N.pdf (332 pages)

3.EP3SL150F780C4N.pdf (456 pages)

Specifications of EP3SL150F1152C3N

Number Of Logic Elements/cells

142500

Number Of Labs/clbs

5700

Total Ram Bits

6390

Number Of I /o

744

Voltage - Supply

0.86 V ~ 1.15 V

Mounting Type

Surface Mount

Operating Temperature

0°C ~ 85°C

Package / Case

1152-FBGA

For Use With

544-2568 - KIT DEVELOPMENT STRATIX III

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Number Of Gates

-

Other names

544-2408
EP3SL150F1152C3NES

Available stocks

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Part Number

Manufacturer

Quantity

Price

Company:

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Part Number:

EP3SL150F1152C3N

Manufacturer:

ALTERA

Quantity:

490

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BOSTOCK HK LIMITED

Part Number:

EP3SL150F1152C3N

Manufacturer:

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Company:

BOSTOCK HK LIMITED

BOSTOCK HK LIMITED

Part Number:

EP3SL150F1152C3N

Manufacturer:

ALTERA

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Company:

BOSTOCK HK LIMITED

BOSTOCK HK LIMITED

Part Number:

EP3SL150F1152C3NES

Manufacturer:

ALTERA

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Table 1–20. PLL Specifications for Stratix III Devices (Part 2 of 3)

f

t

t

t

t

t

t

CLBW

PLL_PSERR

ARESET

INCCJ

OUTPJ_DC

OUTCCJ_DC

OUTPJ_IO

Symbol

(3),

(5),

(5)

(5)

(4)

(8)

PLL closed-loop low bandwidth

PLL closed-loop medium

bandwidth

PLL closed-loop high bandwidth

(6)

Accuracy of PLL phase shift

Minimum pulse width on areset

signal

Input clock cycle to cycle jitter

(F

Input clock cycle to cycle jitter

(F

Period Jitter for dedicated clock

output (F

Period Jitter for dedicated clock

output (F

Cycle to Cycle Jitter for dedicated

clock output

(F

Cycle to Cycle Jitter for dedicated

clock output

(F

Period Jitter for clock output on

regular IO (F

Period Jitter for clock output on

regular IO (F

REF

REF

OUT

OUT

 100 MHz)

< 100 MHz)

100 MHz)

< 100 MHz)

OUT

OUT

100 MHz)

< 100 MHz)

Parameter

OUT

OUT

 100 MHz)

< 100 MHz)

Min

—

—

—

—

10

—

—

—

—

—

—

—

—

V

CCL

Typ

= 1.1 V

0.3

1.5

C2

—

—

—

—

—

—

—

—

—

—

4

±750

Max

0.15

17.5

17.5

±50

175

175

600

—

—

—

—

60

Min

—

—

—

—

10

—

—

—

—

—

—

—

—

V

CCL

C3, I3

Typ

= 1.1 V

0.3

1.5

—

—

—

—

—

—

—

—

—

—

4

±750

0.15

17.5

17.5

Max

±50

175

175

600

—

—

—

—

60

Min

—

—

—

—

10

—

—

—

—

—

—

—

—

V

CCL

C4, I4

Typ

0.3

1.5

= 1.1 V

—

—

—

—

—

—

—

—

—

—

4

±750

Max

0.15

17.5

17.5

±50

175

175

600

—

—

—

—

60

Min

—

—

—

—

10

—

—

—

—

—

—

—

—

V

CCL

Typ

= 1.1 V

0.3

1.5

—

—

—

—

—

—

—

—

—

—

4

±750

Max

0.15

17.5

17.5

±50

175

175

600

—

—

—

—

60

C4L, I4L

Min

—

—

—

—

10

—

—

—

—

—

—

—

—

V

CCL

Typ

0.3

1.5

= 0.9 V

—

—

—

—

—

—

—

—

—

—

4

±500 ps (p-p)

Max

22.5

22.5

±50

225

225

750

0.1

—

—

—

—

75

UI (p-p)

ps (p-p)

ps (p-p)

ps (p-p)

(p-p)

(p-p)

(p-p)

Unit

MHz

MHz

MHz

mUI

mUI

mUI

ps

ns

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