EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 21

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
Switching Characteristics
Periphery Performance
Table 1–25. True and Emulated LVDS Specifications for Stratix III Devices
© July 2010 Altera Corporation
f
(input clock
frequency)—True
Differential I/O
Standards
f
(input clock
frequency)—Single
Ended I/O
Standards
f
(output clock
frequency)
Transmitter
f
LVDS_E_3R -f
(data rate)
HSCLK_in
HSCLK_in
HSCLK_out
HSDR
(data rate)
Symbol
(9)
HSDR
1
Clock boost
factor W = 1 to 40
(3)
Clock boost
factor W = 1 to 40
(3)
SERDES factor
J = 3 to 10
SERDES factor
J = 2, Uses
DDR Register
SERDES factor
J = 1, Uses SDR
Register
SERDES factor
J = 4 to 10
Conditions
This section describes periphery performance, including high-speed I/O and external
memory interface.
I/O performance supports several system interfacing, such as the LVDS high-speed
I/O interface, external memory interface, and the PCI/PCI-X bus interface. For
example, Stratix III devices I/O configured with voltage referenced I/O standards can
achieve up to the stated system interfacing speed as indicated in
Interface Specifications” on page
3.0, 2.5, 1.8, or 1.5 LVTTL/LVCMOS are capable of typical 167 MHz and 1.2 LVCMOS
at 100MHz interfacing frequency with 10pF load.
Actual achievable frequency depends on design- and system-specific factors. You
must perform HSPICE/IBIS simulations based on your specific design and system
setup to determine the maximum achievable frequency in your system.
High-Speed I/O Specifications
Refer to the
specifications.
Table 1–25
—
(8)
lists the true and emulated LVDS specifications for Stratix III devices.
“Glossary” on page 1–326
(4)
(4)
(4)
(4)
5
5
5
—
—
—
—
—
—
—
C2
800
1600
1100
800
800
(4)
(4)
(7)
1–25. General-purpose I/O standards such as 3.3,
(4)
(4)
(4)
(4)
5
5
5
for the definitions of the high-speed timing
C3, I3
—
—
—
—
—
—
—
(Note
717
1250
1100
717
717
(4)
(4)
(7)
1),
(2)
(4)
(4)
(4)
(4)
5
5
5
(Part 1 of 3)
Stratix III Device Handbook, Volume 2
C4, I4
—
—
—
—
—
—
—
717
“External Memory
1250
717
717
800
(4)
(4)
(7)
(4)
(4)
(4)
(4)
5
5
5
C4L, I4L
—
—
—
—
—
—
—
1–21
717
1250
717
717
800
(4)
(4)
(7)
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz