EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 7

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
Electrical Characteristics
Table 1–8. On-Chip Termination Resistance Tolerance Specification for Stratix III Devices
© July 2010 Altera Corporation
R
25- R
25- R
25- R
50- R
50- R
50- R
R
OCT_UNCAL
D
S
S
S
S
S
S
Symbol
3.3, 3.0, 2.5
1.8, 1.5
1.2
3.3, 3.0, 2.5
1.8, 1.5
1.2
The accuracy listed in
temperature changes, the termination resistance value varies.
resistance tolerance for Stratix III OCT.
Table 1–9
calibration. Use
re-calibration.
Equation 1–1. OCT Variation Without Re-Calibration
Notes to
(1) R
(2) R
(3) T is the variation of temperature with respect to the temperature at power-up.
(4) V is the variation of voltage with respect to the V
(5) dR/dT is the percentage change of R
(6) dR/dV is the percentage change of R
Internal series termination without
calibration
Internal series termination without
calibration (25- setting)
Internal series termination without
calibration (25- setting)
Internal series termination without
calibration (25- setting)
Internal series termination without
calibration (50- setting)
Internal series termination without
calibration (50- setting)
Internal series termination without
calibration (50- setting)
Internal differential termination for
LVDS technology (100-setting)
V
CCIO
OCT
SCAL
Equation
.
value calculated from
is the OCT resistance value at power-up.
lists OCT variation with temperature and voltage after power-up
Description
1–1:
Table 1–9
Table 1–7
Equation 1–1
R
O CT
and
=
SCAL
SCAL
Equation 1–1
R
is valid at the time of calibration. If the voltage or
with temperature.
shows the range of OCT resistance with the variation of temperature and
with voltage.
SCAL
V
V
V
V
V
V
V
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO


1
= 3.3, 3.0, 2.5 V
= 1.8, 1.5 V
= 1.2 V
= 3.3, 3.0, 2.5 V
= 1.8, 1.5 V
= 1.2 V
= 2.5 V
CCIO
+
Conditions

at power-up.
dR
------ - T
dT
to determine OCT variation without

(Note 1)



dR
------ -
dV

V
Stratix III Device Handbook, Volume 2
—
±30
±30
±35
±30
±30
±35
Resistance Tolerance

C2


Table 1–8
-15 to 35
±40
±50
±60
±40
±50
±60
C3, I3 C4, I4
lists the
±40
±50
±60
±40
±50
±60
Unit
%
%
%
%
%
%
%
1–7