EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 105
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices
Chapter Revision History
Chapter Revision History
Table 4–10. Chapter Revision History
© May 2009 Altera Corporation
May 2009,
version 1.8
February 2009,
version 1.7
November 2008,
Version 1.6
October 2008,
version 1.5
May 2008,
version 1.4
November 2007,
version 1.3
October 2007,
version 1.2
May 2007,
version 1.1
November 2006,
version 1.0
Date and Revision
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Updated Table 4–2.
■
■
■
Updated Table 4–2, Table 4–9.
Initial Release.
Table 4–10
Updated
Updated
sections.
Updated Figure 4–2, Figure 4–4, and Figure 4–5.
Removed “Referenced Documents” section.
Updated “Byte-Enable Support”, “Address Clock Enable Support”,
“Asynchronous Clear”, “Single Port RAM”, and “Simple Dual-Port Mode”
sections.
Updated Figure 4–1, Figure 4–5, Figure 4–8, Figure 4–10, and
Figure 4–15.
Added Figure 4–2, Figure 4–6, Figure 4–11, Figure 4–14, and
Figure 4–16.
Updated Table 4–1.
Updated “Asynchronous Clear” and “Clocking Modes” section.
Added “Programming File Compatibility” section.
Updated New Document Format.
Updated “Introduction” section.
Updated “TriMatrix Memory Block Types” section.
Updated “Byte-Enable Support” section.
Updated “Mixed Width Support” section.
Updated “Same-Port Read-During-Write Mode” section.
Updated Figure 4–16, Figure 4–17, and Figure 4–18.
Updated “Mixed-Port Read-During-Write Mode” section.
Updated Table 4–1, Table 4–2, and Table 4–4.
Updated Table 4–1.
Added section “Referenced Documents”.
Added live links for references.
Table
“Read/Write Clock Mode”
shows the revision history for this chapter.
4–1.
Changes Made
and
“Simple Dual-Port Mode”
Stratix III Device Handbook, Volume 1
Summary of Changes
—
—
—
—
—
—
—
—
—
4–25
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