EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 111

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 5: DSP Blocks in Stratix III Devices
Simplified DSP Operation
Figure 5–3. Four-Multiplier Adder and Accumulation Capability
© March 2010 Altera Corporation
Input
Data
144
To support commonly found FIR-like structures efficiently, a major addition to the
DSP block in Stratix III is the ability to propagate the result of one Half-Block to the
next Half-Block completely within the DSP block without additional soft logic
overhead. This is achieved by the inclusion of a dedicated addition unit and routing
that adds the 44-bit result of a previous Half-Block with the 44-bit result of the current
block. The 44-bit result is fed either to the next Half-Block or out of the DSP block
through the output register stage. This is shown in
described in later sections.
The combination of a fast, low-latency Four-Multiplier Adder unit and the “chained
cascade” capability of the output-chaining adder provide an optimal FIR and vector
multiplication capability.
To support single-channel type FIR filters efficiently, you can configure one of the
multiplier input’s registers to form a tap delay line input, saving resources and
providing higher system performance.
Half-DSP Block
Figure
5–4. Detailed examples are
Stratix III Device Handbook, Volume 1
44
Result
5–5