EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 116

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

5–10
Input Registers
Stratix III Device Handbook, Volume 1
All of the DSP block registers are triggered by the positive edge of the clock signal and
are cleared upon power up. Each multiplier operand can feed an input register or
directly to the multiplier, bypassing the input registers. (This is configured at compile
time.) The following DSP block signals control the input registers within the DSP
block:
■
■
■
Every DSP block has nine 18-bit data input register banks per half DSP block. Every
half DSP block has the option to use the eight data register banks as inputs to the four
multipliers. The special ninth register bank is a delay register required by modes that
use both the cascade and chainout features of the DSP block and is for balancing the
latency requirements when using the chained cascade feature.
A feature of the input register bank is to support a tap delay line. Therefore, the top
leg of the multiplier input (A) could be driven from general routing or from the
cascade chain, as shown in
clock[3..0]
ena[3..0]
aclr[3..0]
Figure
5–7.
Chapter 5: DSP Blocks in Stratix III Devices
© March 2010 Altera Corporation
DSP Block Resource Descriptions