EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 117

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 5: DSP Blocks in Stratix III Devices
DSP Block Resource Descriptions
Figure 5–7. Input Register of Half-DSP Block
© March 2010 Altera Corporation
You must select whether the A-input comes from general routing or from the cascade
chain at compile time. In cascade mode, the dedicated shift outputs from one
multiplier block directly feeds input registers of the adjacent multiplier below it
(within the same half DSP block) or the first multiplier in the next half DSP block, to
form an 8-tap shift register chain per DSP Block. The DSP block can increase the
length of the shift register chain by cascading to the lower DSP blocks. The dedicated
shift register chain spans a single column, but you can implement longer shift register
chains requiring multiple columns using the regular FPGA routing resources.
datab_2[17..0]
dataa_3[17..0]
datab_3[17..0]
datab_0[17..0]
dataa_1[17..0]
datab_1[17..0]
dataa_2[17..0]
dataa_0[17..0]
loopback
scanina[17..0]
clock[3..0]
ena[3..0]
aclr[3..0]
Register
Delay
signa
signb
+/−
+/−
Stratix III Device Handbook, Volume 1
5–11