EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 120

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

5–14
Round and Saturation Stage
Second Adder and Output Registers
Stratix III Device Handbook, Volume 1
1
The round and saturation logic units are located at the output of the 44-bit
second-stage adder (round logic unit followed by the saturation logic unit). There are
two round and saturation logic units per half DSP block. The input to the round and
saturation logic unit can come from one of the following stages:
■
■
■
■
These stages are discussed in detail in
page
The round and saturation logic unit is controlled by the dynamic round and saturate
signals, respectively. A logic 1 value on the round, saturate, or both enables the
round, saturate, or both logic units.
You can use the round and saturation logic units together or independently.
The second adder register and output register banks are two banks of 44-bit registers
that can also be combined to form larger 72-bit banks to support 36 × 36 output
results.
The outputs of the different stages in the Stratix III devices are routed to the output
registers through an output selection unit. Depending on the operational mode of the
DSP block, the output selection unit selects whether the outputs of the DSP blocks
comes from the outputs of the multiplier block, first-stage adder, pipeline registers,
second-stage adder, or the round and saturation logic unit. The output selection unit
is set automatically by the software, based on the DSP block operational mode you
specified, and has the option to either drive or bypass the output registers. The
exception is when the block is used in shift mode, in which case the user dynamically
controls the output-select multiplexer directly.
When the DSP block is configured in “chained cascaded” output mode, both of the
second-stage adders are used. The first one is used for performing Four-Multiplier
Adder and the second is used for the chainout adder. The outputs of the
Four-Multiplier Adder are routed to the second-stage adder registers before it enters
the chainout adder. The output of the chainout adder goes to the regular output
register bank. Depending on the configuration, the chainout results can be routed to
the input of the next half-block’s chainout adder input or to the general fabric
(functioning as regular output registers). Refer to
on page 5–15
Output of the multiplier (independent multiply mode in 18 × 18)
Output of the first-stage adder (Two-Multiplier Adder)
Output of the pipeline registers
Output of the second-stage adder (Four-Multiplier Adder, Multiply-Accumulate
Mode in 18 × 18)
5–15.
for details.
“Operational Mode Descriptions” on
“Operational Mode Descriptions”
Chapter 5: DSP Blocks in Stratix III Devices
© March 2010 Altera Corporation
DSP Block Resource Descriptions