EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 121

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 5: DSP Blocks in Stratix III Devices
Operational Mode Descriptions
Operational Mode Descriptions
Independent Multiplier Modes
9-, 12-, and 18-Bit Multiplier
Figure 5–8. 18-Bit Independent Multiplier Mode for Half-DSP Block
© March 2010 Altera Corporation
dataa_0[17..0]
datab_0[17..0]
dataa_1[17..0]
datab_1[17..0]
The second-stage and output registers are triggered by the positive edge of the clock
signal and are cleared on power up. The following DSP block signals control the
output registers within the DSP block:
■
■
■
The various modes of operation are discussed below.
In independent input and output multiplier mode, the DSP block performs individual
multiplication operations for general-purpose multipliers.
You can configure each DSP block multiplier for 9-, 12-, or 18-bit multiplication. A
single DSP block can support up to eight individual 9 × 9 multipliers, six 12 × 12
multipliers, or up to four individual 18 × 18 multipliers. For operand widths up to
9 bits, a 9 × 9 multiplier is implemented. For operand widths from 10 to 12 bits, a
12 × 12 multiplier is implemented, and for operand widths from 13 to 18 bits, an
18 × 18 multiplier is implemented. This is done by the Quartus II software by
zero-padding the LSBs.
the independent multiplier operation mode.
clock[3..0]
ena[3..0]
aclr[3..0]
clock[3..0]
ena[3..0]
aclr[3..0]
18
18
18
18
Half-DSP Block
output_saturate
Figure
output_round
signb
signa
5–8,
Figure
5–9, and
Figure 5–10
36
36
overflow
Stratix III Device Handbook, Volume 1
result_1[ ]
result_0[ ]
show the DSP block in
5–15