EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 123
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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Chapter 5: DSP Blocks in Stratix III Devices
Operational Mode Descriptions
Figure 5–10. 9-Bit Independent Multiplier Mode for Half-Block
© March 2010 Altera Corporation
1
dataa_1[8..0]
datab_1[8..0]
dataa_3[8..0]
datab_3[8..0]
dataa_0[8..0]
datab_0[8..0]
dataa_2[8..0]
datab_2[8..0]
The multiplier operands can accept signed integers, unsigned integers, or a
combination of both. You can change the signa and signb signals dynamically and
can be registered in the DSP block. Additionally, the multiplier inputs and result can
be registered independently. You can use the pipeline registers within the DSP block
to pipeline the multiplier result, increasing the performance of the DSP block.
The round and saturation logic unit is supported for the 18-bit independent multiplier
mode only.
clock[3..0]
ena[3..0]
aclr[3..0]
9
9
9
9
9
9
9
9
Half-DSP Block
signa
signb
18
18
18
18
Stratix III Device Handbook, Volume 1
result_0[ ]
result_1[ ]
result_2[ ]
result_3[ ]
5–17
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