EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 131

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 5: DSP Blocks in Stratix III Devices
Operational Mode Descriptions
Four-Multiplier Adder
Figure 5–17. Four-Multiplier Adder Mode for Half-DSP Block
© March 2010 Altera Corporation
dataa_0[ ]
datab_0[ ]
dataa_1[ ]
datab_1[ ]
datab_2[ ]
dataa_3[ ]
datab_3[ ]
dataa_2[ ]
In the four-multiplier adder configuration shown in
implement two four-multiplier adders (one four-multiplier adder per half DSP block).
These modes are useful for implementing one-dimensional and two-dimensional
filtering applications. The four-multiplier adder is performed in two addition stages.
The outputs of two of the four multipliers are initially summed in the two first-stage
adder blocks. The results of these two adder blocks are then summed in the
second-stage adder block to produce the final four-multiplier adder result, as shown
by
The four-multiplier adder mode supports the round and saturation logic unit. You can
use the pipeline registers and output registers within the DSP block to pipeline the
multiplier-adder result, increasing the performance of the DSP block.
Equation 5–2
Half-DSP Block
clock[3..0]
ena[3..0]
aclr[3..0]
and
Equation
+
+
output_saturate
output_round
5–3.
signa
signb
+
Figure
Stratix III Device Handbook, Volume 1
5–17, the DSP block can
overflow
result[ ]
5–25